公开(公告)号：US20050078548A1

公开(公告)日：2005-04-14

申请号：US10951881

申请日：2004-09-29

申请人： Young-gu Kang ,  Jong-hyun Choi ,  Woo-seop Jeong ,  Ki-ho Jang ,  Jung-yong Choi

发明人： Young-gu Kang ,  Jong-hyun Choi ,  Woo-seop Jeong ,  Ki-ho Jang ,  Jung-yong Choi

IPC分类号： G11C11/409 ,  G11C7/00 ,  G11C7/10 ,  G11C29/46

CPC分类号： G11C7/1045 ,  G11C29/46

摘要： A memory system, memory device, and method for setting an operating mode of a memory device include a memory cell array; row and column decoders which select a row and a column of the memory cell array, respectively, according to a multi-bit address signal; and a mode control circuit which receives at least one bit from the multi-bit address signal used in the selection of the row or the column, and which sets an operating mode of the memory device according to the at least one bit, wherein the operating mode is one of a burst length mode, a DLL reset mode, a test mode, a CAS latency mode, and a burst type mode.

摘要翻译： 用于设置存储器件的操作模式的存储器系统，存储器件和方法包括存储器单元阵列; 行和列解码器，其分别根据多位地址信号选择存储单元阵列的行和列; 以及模式控制电路，其从在行或列的选择中使用的多位地址信号接收至少一个位，并且根据至少一个位设置存储器件的操作模式，其中操作 模式是突发长度模式，DLL复位模式，测试模式，CAS延迟模式和突发类型模式之一。

公开(公告)号：US07042800B2

公开(公告)日：2006-05-09

申请号：US10951881

申请日：2004-09-29

申请人： Young-gu Kang ,  Jong-hyun Choi ,  Woo-seop Jeong ,  Ki-ho Jang ,  Jung-yong Choi

发明人： Young-gu Kang ,  Jong-hyun Choi ,  Woo-seop Jeong ,  Ki-ho Jang ,  Jung-yong Choi

IPC分类号： G11C8/00

CPC分类号： G11C7/1045 ,  G11C29/46

摘要： A memory system, memory device, and method for setting an operating mode of a memory device include a memory cell array; row and column decoders which select a row and a column of the memory cell array, respectively, according to a multi-bit address signal; and a mode control circuit which receives at least one bit from the multi-bit address signal used in the selection of the row or the column, and which sets an operating mode of the memory device according to the at least one bit, wherein the operating mode is one of a burst length mode, a DLL reset mode, a test mode, a CAS latency mode, and a burst type mode.

摘要翻译： 用于设置存储器件的操作模式的存储器系统，存储器件和方法包括存储器单元阵列; 行和列解码器，其分别根据多位地址信号选择存储单元阵列的行和列; 以及模式控制电路，其从在行或列的选择中使用的多位地址信号接收至少一个位，并且根据至少一个位设置存储器件的操作模式，其中操作 模式是突发长度模式，DLL复位模式，测试模式，CAS延迟模式和突发类型模式之一。

公开(公告)号：US20070188194A1

公开(公告)日：2007-08-16

申请号：US11700907

申请日：2007-02-01

申请人： Hui-kap Yang ,  Young-gu Kang ,  Ki-chul Chun ,  Eun-sung Seo ,  Mi-jo Kim

发明人： Hui-kap Yang ,  Young-gu Kang ,  Ki-chul Chun ,  Eun-sung Seo ,  Mi-jo Kim

IPC分类号： H03K19/0175

CPC分类号： H03K19/018528

摘要： A level shifter circuit and method thereof are provided. The example level shifter circuit may include a pull-up drive unit driving an output node from a first voltage to a second voltage in response to an input signal, a target voltage for the second voltage higher than a target voltage for the first voltage and the input signal based on the first voltage and a third voltage and a pull-down drive unit driving the output node to the third voltage in response to the input signal, the pull-up and pull-down drive units adjusting current levels of at least one of a pull-up current flowing through the pull-up drive unit and a pull-down current flowing through the pull-down drive unit based on whether the pull-up drive unit and the pull-down drive unit are operating concurrently. The example method may include pull-up driving an output node from a first voltage to a second voltage in response to an input signal, a target voltage for the second voltage higher than a target voltage for the first voltage and the input signal based on the first voltage and a third voltage, pull-down driving the output node to the third voltage in response to the input signal, determining whether the pull-up and pull-down driving operations are performed concurrently and adjusting current levels of at least one of a pull-up current and a pull-down current based on the determining step.

摘要翻译： 提供了一种电平移位器电路及其方法。 示例电平移位器电路可以包括上拉驱动单元，其响应于输入信号将输出节点从第一电压驱动到第二电压，第二电压的目标电压高于第一电压的目标电压， 基于所述第一电压的输入信号和第三电压和下拉驱动单元，所述下拉驱动单元响应于所述输入信号将所述输出节点驱动到所述第三电压，所述上拉和下拉驱动单元调整至少一个 基于上拉驱动单元和下拉驱动单元是否同时工作，流过上拉驱动单元的上拉电流和流经下拉驱动单元的下拉电流。 示例性方法可以包括响应于输入信号将输出节点从第一电压驱动到第二电压的上拉，用于第二电压的目标电压高于第一电压的目标电压，以及基于 第一电压和第三电压，响应于输入信号将输出节点下拉驱动到第三电压，确定是否同时执行上拉和下拉驱动操作，并且调整以下中的至少一个的电流水平 基于确定步骤的上拉电流和下拉电流。

公开(公告)号：US07139847B2

公开(公告)日：2006-11-21

申请号：US10900506

申请日：2004-07-27

申请人： Yong-jin Park ,  Sang-keun Park ,  Hong Kim ,  Young-gu Kang

发明人： Yong-jin Park ,  Sang-keun Park ,  Hong Kim ,  Young-gu Kang

IPC分类号： G06F3/00

CPC分类号： G11C7/1045 ,  G11C7/1078

摘要： A semiconductor memory device having an externally controllable input and output mode is provided. The semiconductor memory device includes a first and second plurality of pads and an input and output mode set circuit electrically connected to the first plurality of pads and the second plurality of pads, for generating a plurality of input and output mode signals. The input and output mode set circuit cuts off signals received from the first plurality of pads, controls the level of each of the input and output mode signals to be at either a logic high level and a logic low level, and sets the input and output mode when a voltage higher than the supply voltage of the semiconductor memory device is applied to one of the second plurality of pads in a test mode. The high voltage is not applied to the second plurality of pads and the input and output mode set circuit controls the level of the input and output mode signals to be at either a logic high level or a logic low level, and thus sets the semiconductor memory device to have one input and output mode responsive to signals received from the plurality of pads, during a normal operation. Accordingly, it is possible to externally change the input and output mode of the semiconductor memory device.

摘要翻译： 提供具有外部可控输入和输出模式的半导体存储器件。 半导体存储器件包括第一和第二多个焊盘以及电连接到第一多个焊盘和第二多个焊盘的输入和输出模式设置电路，用于产生多个输入和输出模式信号。 输入和输出模式设置电路切断从第一多个焊盘接收的信号，将每个输入和输出模式信号的电平控制在逻辑高电平和逻辑低电平，并设置输入和输出 当在测试模式中将高于半导体存储器件的电源电压的电压施加到第二多个焊盘中的一个焊盘时， 高电压不施加到第二多个焊盘，并且输入和输出模式设置电路将输入和输出模式信号的电平控制在逻辑高电平或逻辑低电平，从而将半导体存储器 在正常操作期间具有响应于从所述多个焊盘接收的信号的一个输入和输出模式的装置。 因此，可以从外部改变半导体存储器件的输入和输出模式。

公开(公告)号：US20070165464A1

公开(公告)日：2007-07-19

申请号：US11593967

申请日：2006-11-07

申请人： Hui-kap Yang ,  Young-gu Kang

发明人： Hui-kap Yang ,  Young-gu Kang

IPC分类号： G11C7/00

CPC分类号： G11C7/20 ,  G11C5/14 ,  G11C2207/2227

摘要： A memory device for early stabilization and rapid increase of a power level after deep power down exit includes a deep power down exit pulse generator, a deep power down exit mode signal generator, a current driving unit, a controller and a voltage generator. The deep power down exit pulse generator generates a deep power down exit pulse signal having a predetermined pulse width in response to a deep power down command. The deep power down exit mode signal generator generates a deep power down exit mode bias signal in response to the deep power down exit pulse signal. The current driving unit generates a deep power down exit mode reference voltage in response to the deep power down exit mode bias signal and a reference signal. The controller generates an enable signal in response to the deep power down exit mode bias signal or an active command. The voltage generator compares the deep power down exit mode reference voltage to an internal power supply voltage in response to the enable signal and outputs the internal power supply voltage. The memory device previously generates the internal power supply voltage, which is used in the active mode, in a deep power down exit mode before an active command is applied to the memory device, and thus a power-up ensuring time after deep power down mode exit can be reduced.

摘要翻译： 用于早期稳定并且在深度断电出口之后功率电平快速增加的存储器件包括深度断电输出脉冲发生器，深度掉电输出模式信号发生器，电流驱动单元，控制器和电压发生器。 深度断电输出脉冲发生器响应于深度断电命令产生具有预定脉冲宽度的深度掉电输出脉冲信号。 深度掉电退出模式信号发生器响应深度掉电输出脉冲信号产生深度掉电输出模式偏置信号。 电流驱动单元响应于深度掉电输出模式偏置信号和参考信号产生深度断电退出模式参考电压。 控制器响应于深度掉电退出模式偏置信号或有效命令产生使能信号。 电压发生器根据使能信号将深度掉电退出模式参考电压与内部电源电压进行比较，并输出内部电源电压。 存储器件在有效命令被施加到存储器件之前，先前以深度掉电退出模式生成在活动模式中使用的内部电源电压，从而在深度断电模式之后确保上电确保时间 出口可以减少。

公开(公告)号：US07548482B2

公开(公告)日：2009-06-16

申请号：US11593967

申请日：2006-11-07

申请人： Hui-kap Yang ,  Young-gu Kang

发明人： Hui-kap Yang ,  Young-gu Kang

IPC分类号： G11C7/00

CPC分类号： G11C7/20 ,  G11C5/14 ,  G11C2207/2227

摘要： A memory device for early stabilization and rapid increase of a power level after deep power down exit includes a deep power down exit pulse generator, a deep power down exit mode signal generator, a current driving unit, a controller and a voltage generator. The deep power down exit pulse generator generates a deep power down exit pulse signal having a predetermined pulse width in response to a deep power down command. The deep power down exit mode signal generator generates a deep power down exit mode bias signal in response to the deep power down exit pulse signal. The current driving unit generates a deep power down exit mode reference voltage in response to the deep power down exit mode bias signal and a reference signal. The controller generates an enable signal in response to the deep power down exit mode bias signal or an active command. The voltage generator compares the deep power down exit mode reference voltage to an internal power supply voltage in response to the enable signal and outputs the internal power supply voltage. The memory device previously generates the internal power supply voltage, which is used in the active mode, in a deep power down exit mode before an active command is applied to the memory device, and thus a power-up ensuring time after deep power down mode exit can be reduced.

摘要翻译： 用于早期稳定并且在深度断电出口之后功率电平快速增加的存储器件包括深度断电输出脉冲发生器，深度掉电输出模式信号发生器，电流驱动单元，控制器和电压发生器。 深度断电输出脉冲发生器响应于深度断电命令产生具有预定脉冲宽度的深度掉电输出脉冲信号。 深度掉电退出模式信号发生器响应深度掉电输出脉冲信号产生深度掉电输出模式偏置信号。 电流驱动单元响应于深度掉电输出模式偏置信号和参考信号产生深度断电退出模式参考电压。 控制器响应于深度掉电退出模式偏置信号或有效命令产生使能信号。 电压发生器根据使能信号将深度掉电退出模式参考电压与内部电源电压进行比较，并输出内部电源电压。 存储器件在有效命令被施加到存储器件之前，先前以深度掉电退出模式生成在活动模式中使用的内部电源电压，从而在深度断电模式之后确保上电确保时间 出口可以减少。

公开(公告)号：US06845407B1

公开(公告)日：2005-01-18

申请号：US09621925

申请日：2000-07-24

申请人： Yong-Jin Park ,  Sang-keun Park ,  Hong Kim ,  Young-gu Kang

发明人： Yong-Jin Park ,  Sang-keun Park ,  Hong Kim ,  Young-gu Kang

IPC分类号： G01R31/26 ,  G01R31/28 ,  G11C7/10 ,  G11C11/401 ,  G11C11/406 ,  G11C11/413 ,  G11C11/417 ,  G11C16/06 ,  G11C17/00 ,  G11C17/18 ,  G11C29/14 ,  G06F3/00

CPC分类号： G11C7/1045 ,  G11C7/1078

摘要： A semiconductor memory device having an externally controllable input and output mode is provided. The semiconductor memory device includes a first and second plurality of pads and an input and output mode set circuit electrically connected to the first plurality of pads and the second plurality of pads, for generating a plurality of input and output mode signals. The input and output mode set circuit cuts off signals received from the first plurality of pads, controls the level of each of the input and output mode signals to be at either a logic high level and a logic low level, and sets the input and output mode when a voltage higher than the supply voltage of the semiconductor memory device is applied to one of the second plurality of pads in a test mode. The high voltage is not applied to the second plurality of pads and the input and output mode set circuit controls the level of the input and output mode signals to be at either a logic high level or a logic low level, and thus sets the semiconductor memory device to have one input and output mode responsive to signals received from the plurality of pads, during a normal operation. Accordingly, it is possible to externally change the input and output mode of the semiconductor memory device.

摘要翻译： 提供具有外部可控输入和输出模式的半导体存储器件。 半导体存储器件包括第一和第二多个焊盘以及电连接到第一多个焊盘和第二多个焊盘的输入和输出模式设置电路，用于产生多个输入和输出模式信号。 输入和输出模式设置电路切断从第一多个焊盘接收的信号，将每个输入和输出模式信号的电平控制在逻辑高电平和逻辑低电平，并设置输入和输出 当在测试模式中将高于半导体存储器件的电源电压的电压施加到第二多个焊盘中的一个焊盘时， 高电压不施加到第二多个焊盘，并且输入和输出模式设置电路将输入和输出模式信号的电平控制在逻辑高电平或逻辑低电平，从而将半导体存储器 在正常操作期间具有响应于从所述多个焊盘接收的信号的一个输入和输出模式的装置。 因此，可以从外部改变半导体存储器件的输入和输出模式。

公开(公告)号：US20050001244A1

公开(公告)日：2005-01-06

申请号：US10900506

申请日：2004-07-27

申请人： Yong-jin Park ,  Sang-keun Park ,  Hong Kim ,  Young-gu Kang

发明人： Yong-jin Park ,  Sang-keun Park ,  Hong Kim ,  Young-gu Kang

IPC分类号： G01R31/26 ,  G01R31/28 ,  G11C7/10 ,  G11C11/401 ,  G11C11/406 ,  G11C11/413 ,  G11C11/417 ,  G11C16/06 ,  G11C17/00 ,  G11C17/18 ,  G11C29/14 ,  G06G7/12

CPC分类号： G11C7/1045 ,  G11C7/1078

摘要： A semiconductor memory device having an externally controllable input and output mode is provided. The semiconductor memory device includes a first and second plurality of pads and an input and output mode set circuit electrically connected to the first plurality of pads and the second plurality of pads, for generating a plurality of input and output mode signals. The input and output mode set circuit cuts off signals received from the first plurality of pads, controls the level of each of the input and output mode signals to be at either a logic high level and a logic low level, and sets the input and output mode when a voltage higher than the supply voltage of the semiconductor memory device is applied to one of the second plurality of pads in a test mode. The high voltage is not applied to the second plurality of pads and the input and output mode set circuit controls the level of the input and output mode signals to be at either a logic high level or a logic low level, and thus sets the semiconductor memory device to have one input and output mode responsive to signals received from the plurality of pads, during a normal operation. Accordingly, it is possible to externally change the input and output mode of the semiconductor memory device.