-
1.发明授权Nonvolatile semiconductor memory device, semiconductor device and method of manufacturing nonvolatile semiconductor memory device 有权非易失性半导体存储器件，半导体器件和制造非易失性半导体存储器件的方法公开(公告)号：US07462905B2
公开(公告)日：2008-12-09
申请号：US11495455
申请日：2006-07-31
IPC分类号： H01L29/788 , H01L21/8239 , H01L23/528
CPC分类号： H01L27/115 , H01L21/28273 , H01L21/764 , H01L27/11521
摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate, a first floating gate formed on a main surface of the semiconductor substrate, a second floating gate formed on the main surface of the semiconductor substrate, a first control gate formed on the first floating gate, a second control gate formed on the second floating gate, an interlayer insulating film, and a gap formed in the interlayer insulating film in at least a portion located between the first and second floating gates. Accordingly, a nonvolatile semiconductor memory device for which variations in threshold voltage of a memory cell can be suppressed and an appropriate read operation can be carried out, as well as a method of manufacturing the nonvolatile semiconductor memory device are provided. Further, a capacitance formed between interconnect lines can be reduced and the drive speed can be improved.
摘要翻译： 非易失性半导体存储器件包括半导体衬底，形成在半导体衬底的主表面上的第一浮置栅极，形成在半导体衬底的主表面上的第二浮置栅极，形成在第一浮动栅极上的第一控制栅极， 形成在第二浮栅上的第二控制栅极，层间绝缘膜，以及形成在位于第一和第二浮栅之间的至少一部分的层间绝缘膜中的间隙。 因此，提供了可以抑制存储单元的阈值电压的变化并且可以执行适当的读取操作的非易失性半导体存储器件以及制造非易失性半导体存储器件的方法。 此外，可以降低在互连线之间形成的电容，并且可以提高驱动速度。
-
公开(公告)号：US20090075471A1
公开(公告)日：2009-03-19
申请号：US12267922
申请日：2008-11-10
IPC分类号： H01L21/768
CPC分类号： H01L27/115 , H01L21/764 , H01L27/11521 , H01L29/40114
摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate, a first floating gate formed on a main surface of the semiconductor substrate, a second floating gate formed on the main surface of the semiconductor substrate, a first control gate formed on the first floating gate, a second control gate formed on the second floating gate, an interlayer insulating film, and a gap formed in the interlayer insulating film in at least a portion located between the first and second floating gates. Accordingly, a nonvolatile semiconductor memory device for which variations in threshold voltage of a memory cell can be suppressed and an appropriate read operation can be carried out, as well as a method of manufacturing the nonvolatile semiconductor memory device are provided. Further, a capacitance formed between interconnect lines can be reduced and the drive speed can be improved.
摘要翻译： 非易失性半导体存储器件包括半导体衬底，形成在半导体衬底的主表面上的第一浮置栅极，形成在半导体衬底的主表面上的第二浮置栅极，形成在第一浮动栅极上的第一控制栅极， 形成在第二浮栅上的第二控制栅极，层间绝缘膜，以及形成在位于第一和第二浮栅之间的至少一部分的层间绝缘膜中的间隙。 因此，提供了可以抑制存储单元的阈值电压的变化并且可以执行适当的读取操作的非易失性半导体存储器件以及制造非易失性半导体存储器件的方法。 此外，可以降低在互连线之间形成的电容，并且可以提高驱动速度。
-
3.发明申请Nonvolatile semiconductor memory device, semiconductor device and method of manufacturing nonvolatile semiconductor memory device 有权非易失性半导体存储器件，半导体器件和制造非易失性半导体存储器件的方法公开(公告)号：US20070063256A1
公开(公告)日：2007-03-22
申请号：US11495455
申请日：2006-07-31
IPC分类号： H01L21/8238
CPC分类号： H01L27/115 , H01L21/28273 , H01L21/764 , H01L27/11521
摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate, a first floating gate formed on a main surface of the semiconductor substrate, a second floating gate formed on the main surface of the semiconductor substrate, a first control gate formed on the first floating gate, a second control gate formed on the second floating gate, an interlayer insulating film, and a gap formed in the interlayer insulating film in at least a portion located between the first and second floating gates. Accordingly, a nonvolatile semiconductor memory device for which variations in threshold voltage of a memory cell can be suppressed and an appropriate read operation can be carried out, as well as a method of manufacturing the nonvolatile semiconductor memory device are provided. Further, a capacitance formed between interconnect lines can be reduced and the drive speed can be improved.
摘要翻译： 非易失性半导体存储器件包括半导体衬底，形成在半导体衬底的主表面上的第一浮置栅极，形成在半导体衬底的主表面上的第二浮置栅极，形成在第一浮动栅极上的第一控制栅极， 形成在第二浮栅上的第二控制栅极，层间绝缘膜，以及形成在位于第一和第二浮栅之间的至少一部分的层间绝缘膜中的间隙。 因此，提供了可以抑制存储单元的阈值电压的变化并且可以执行适当的读取操作的非易失性半导体存储器件以及制造非易失性半导体存储器件的方法。 此外，可以降低在互连线之间形成的电容，并且可以提高驱动速度。
-
公开(公告)号：US08896092B2
公开(公告)日：2014-11-25
申请号：US13344662
申请日：2012-01-06
IPC分类号： H01L23/52 , H01L23/525 , H01L27/02 , H01L23/62 , H01L25/16
CPC分类号： H01L23/5252 , H01L23/62 , H01L25/167 , H01L27/0248 , H01L2924/0002 , H01L2924/00
摘要： An anti-fuse element that includes a capacitance unit having an insulation layer and at least a pair of electrode layers formed on upper and lower surfaces of the insulation layer. The capacitance unit has a protection function against electrostatic discharge. Because the capacitance unit has a protection function against electrostatic discharge, an anti-fuse element can be provided which is less likely to cause insulation breakdown due to electrostatic discharge at the time of, for example, mounting a component.
摘要翻译： 一种抗熔丝元件，包括具有绝缘层的电容单元和形成在绝缘层的上表面和下表面上的至少一对电极层。 电容单元具有防静电放电的保护功能。 由于电容单元具有防静电放电的保护功能，所以可以提供抗熔丝元件，其不太可能由于例如安装元件时的静电放电引起绝缘击穿。
-
公开(公告)号：US20100118468A1
公开(公告)日：2010-05-13
申请号：US12690480
申请日：2010-01-20
摘要： A thin film capacitor including a substrate, a capacitor portion having an upper conductor, a lower conductor, and a dielectric thin film, and a resin protective layer for protecting the capacitor portion. A barrier layer is interposed between the capacitor portion and the resin protective layer. The barrier layer includes a crystalline dielectric barrier layer formed in contact with the capacitor portion and having the same composition system as the dielectric thin film, and an amorphous inorganic barrier layer formed on the surface of the crystalline dielectric barrier layer and composed of silicon nitride having non-conductivity. The inorganic barrier layer prevents deterioration in the properties of the dielectric thin film by blocking diffusion of the constituent elements of the inorganic barrier layer toward the capacitor portion.
摘要翻译： 包括基板，具有上导体的电容器部分，下导体和电介质薄膜的薄膜电容器和用于保护电容器部分的树脂保护层。 在电容器部分和树脂保护层之间插入阻挡层。 阻挡层包括形成为与电容器部分接触并且具有与电介质薄膜相同的组成系统的结晶介质阻挡层，以及形成在结晶介质阻挡层的表面上并由氮化硅构成的无定形无机阻挡层， 非导电性。 无机阻挡层通过阻止无机阻挡层的构成元件朝向电容器部分的扩散来防止电介质薄膜的性质的劣化。
-
公开(公告)号：US06555165B2
公开(公告)日：2003-04-29
申请号：US09737186
申请日：2000-12-14
申请人： Yutaka Takeshima
发明人： Yutaka Takeshima
IPC分类号： C23C1640
CPC分类号： C23C16/45593 , C23C16/18 , C23C16/4412 , C23C16/45561
摘要： A method for forming a thin film comprises the steps of: forming a first thin film using a raw material which comprises an adduct of metal &bgr;-diketonate and adduct-forming material by a metal organic chemical vapor deposition (MOCVD) method; associating metal &bgr;-diketonate dissociated from the adduct in the raw material with an adduct-forming material to regenerate the raw material; and forming a second thin film using the regenerated raw material by the MOCVD method.
-
公开(公告)号：US06462933B2
公开(公告)日：2002-10-08
申请号：US09773642
申请日：2001-01-31
申请人： Yutaka Takeshima , Yukio Sakabe
发明人： Yutaka Takeshima , Yukio Sakabe
IPC分类号： H01G4228
CPC分类号： H01G4/306
摘要： A thin film multilayer capacitor and a method for mounting it are provide wherein the capacitor is small and thin, can furnish a large capacitance, and is hard to be damaged at the time of mounting on a wiring substrate. The thin film multilayer capacitor 10 comprises a substrate 12 and a laminated body 14 formed thereon. The laminated body 14 is formed by laminating electrode layers 16 and dielectric layers 18. The electrode layers 16 are divided into a first group of electrode layers 16a and a second group of electrode layers 16b by the dielectric layers 18. The electrode layers 16a of the first group and the electrode layers 16b of the second group are laminated in an alternate manner with the dielectric layers 18 intervening therebetween, the plurality of electrode layers 16a of the first group are connected with each other, and the plurality of electrode layers 16b of the second group are also connected with each other. A protective film 20 is formed on the surrounding surfaces of the laminated body 14, and solder bumps 24 are formed at the openings 22.
摘要翻译： 提供薄膜叠层电容器及其安装方法，其中电容器体积小而薄，可以提供大的电容，并且在安装在布线基板上时难以损坏。 薄膜叠层电容器10包括基板12和形成在其上的层叠体14。 层叠体14通过层叠电极层16和电介质层18而形成。电极层16通过电介质层18分为第一组电极层16a和第二组电极层16b。电极层16a 第一组和第二组的电极层16b以介于其间的电介质层18交替地叠层，第一组的多个电极层16a彼此连接，并且多个电极层16b 第二组也相互连接。 在层叠体14的周围形成保护膜20，在开口部22形成有焊锡凸块24。
-
公开(公告)号：US20110309472A1
公开(公告)日：2011-12-22
申请号：US13218561
申请日：2011-08-26
IPC分类号： H01L23/525
CPC分类号： H01L23/5252 , H01L23/62 , H01L25/0756 , H01L25/167 , H01L33/0095 , H01L2224/32225 , H05B37/03
摘要： An anti-fuse element that includes first and second electrode films on both of upper and lower surfaces of a dielectric film to form an element body. When an operation voltage is applied to the element body, the first and second electrode films are fused by heat generation by electrification, whereby balled portions are formed, and a crack also occurs in the dielectric film. Then, the balled portions are enlarged, the dielectric film is completely divided, and the first and second electrode films are welded and integrated with each other in a mode of tangling end portions of the dielectric film, and form bonded portions that turn the anti-fuse element into a conducting state.
摘要翻译： 一种抗熔丝元件，其在电介质膜的上表面和下表面都包括第一和第二电极膜，以形成元件体。 当向元件体施加操作电压时，通过带电产生的热量来熔化第一和第二电极膜，由此形成球形部分，并且在电介质膜中也发生裂纹。 然后，扩大球状部分，电介质膜被完全分开，并且第一和第二电极膜以电介质膜的端部缠结的方式彼此焊接并一体化，并且形成接合部分， 熔丝元件变成导通状态。
-
公开(公告)号：US20110110016A1
公开(公告)日：2011-05-12
申请号：US13009395
申请日：2011-01-19
申请人： Yutaka Takeshima , Masanobu Nomura , Takeshi Inao
发明人： Yutaka Takeshima , Masanobu Nomura , Takeshi Inao
IPC分类号： H01G4/06
CPC分类号： H01G4/228 , H01G4/232 , H01G4/33 , H01L23/5223 , H01L24/11 , H01L27/016 , H01L28/40 , H01L2224/05001 , H01L2224/05008 , H01L2224/05027 , H01L2224/05567 , H01L2224/05655 , H01L2924/00014 , H01L2924/12044 , H01L2924/14 , H01L2924/15787 , H01L2924/3011 , H01L2924/00 , H01L2224/05099
摘要： A thin-film capacitor and a method for making the thin-film capacitor having a structure that can prevent vertical stress acting on outer connecting terminals, such as bumps, from concentrating on electrode layers, and capable of easily increasing the equivalent series resistance to a desired value. The thin-film capacitor includes a substrate, a capacitor unit disposed above the substrate and composed of at least one dielectric thin film and two electrode layers, a protective layer covering at least part of the capacitor unit, a lead conductor electrically connected to one of the electrode layers of the capacitor unit, and a bump disposed above the lead conductor. The lead conductor includes a connecting part disposed in an opening in the protective layer and electrically connected to one of the electrode layers of the capacitor unit, and a wiring part extending over the protective layer. The bump is disposed above the wiring part.
摘要翻译： 薄膜电容器和薄膜电容器的制造方法，其具有能够防止作用在外部连接端子（例如凸块）的垂直应力集中在电极层上的结构，并且能够容易地将等效的串联电阻提高到 所需值。 薄膜电容器包括基板，设置在基板上方并由至少一个电介质薄膜和两个电极层构成的电容器单元，覆盖电容器单元的至少一部分的保护层，电连接到 电容器单元的电极层和设置在引线导体上方的凸块。 引线导体包括设置在保护层的开口中并与电容器单元的电极层中的一个电连接的连接部分和在保护层上延伸的布线部分。 凸块设置在布线部分上方。
-
公开(公告)号：US20100252527A1
公开(公告)日：2010-10-07
申请号：US12813774
申请日：2010-06-11
申请人： Yutaka Takeshima , Masanobu Nomura
发明人： Yutaka Takeshima , Masanobu Nomura
IPC分类号： H01B13/00
CPC分类号： H01G4/33 , H01G4/228 , H01G4/306 , H01L27/016 , H01L28/91
摘要： A method for producing a thin film laminated capacitor that makes it possible to reduce the number of operations for etching its electrode layers and its dielectric layers. On a substrate, a capacitor part is formed wherein n electrode layers and (n−1) dielectric layers are alternately laminated onto each other, wherein n is 4 or more. The capacitor part is etched from the same side k times. In any ith etching operation, through holes are formed in an amount corresponding to respective ai layers of the electrode layers and the dielectric layers. At least one of ai's is set to 2 or more, and k is made smaller than n−1, thereby making it possible to make the 2nd to nth layers of the electrode layers from the etching starting side exposed at the bottom surfaces of the through holes.
摘要翻译： 一种制造薄膜层压电容器的方法，其可以减少用于蚀刻其电极层及其电介质层的操作次数。 在基板上，形成电容器部，其中n个电极层和（n-1）个介电层交替层叠在一起，其中n为4以上。 电容器部分从同一侧刻蚀k次。 在任何第i蚀刻操作中，以对应于电极层和电介质层的各个层的量形成通孔。 将ai中的至少一个设定为2以上，并使k小于n-1，从而可以使从第1至第n层的电极层的蚀刻开始侧暴露于贯通孔的底面 孔。
-
-
-
-
-
-
-
-
-
搜索结果
31 条记录 (耗时 0.02 秒)
