公开(公告)号：US08458761B2

公开(公告)日：2013-06-04

申请号：US10167242

申请日：2002-06-11

Applicant: Rodrigo Cordero ,  Patrice Woodward

Inventor： Rodrigo Cordero ,  Patrice Woodward

IPC: H04N7/16

CPC classification number: H04N21/42615 ,  H04N21/426 ,  H04N21/434 ,  H04N21/4341 ,  H04N21/4345

Abstract: A receiver for receiving a data stream comprises a filtering arrangement for filtering said received data stream and a processor. The filtering arrangement is arranged to load at least a part of said data stream, to filter at least part of said data stream and to read at least part of said data stream. The filtering arrangement has a first mode in which said steps are carried out and a second mode in which said processor is arranged to interrupt the steps carried out by said filtering arrangement.

公开(公告)号：US08412989B2

公开(公告)日：2013-04-02

申请号：US13438658

申请日：2012-04-03

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G01R31/28 ,  G01R31/02 ,  G11C29/00

CPC classification number: G01R31/318563 ,  G01R31/318536

Abstract: An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a test mode in which one or more of the plurality of portions are testable, wherein the circuit has a reset mode which has priority over the test mode.

Abstract translation: 一种集成电路，包括（i）多个部分，每个部分包括测试控制电路; 以及（ii）布置成接收测试信号的至少一个测试输入，所述电路具有其中所述多个部分中的一个或多个部分是可测试的测试模式，其中所述电路具有优于所述测试模式的重置模式。

公开(公告)号：US20120266037A1

公开(公告)日：2012-10-18

申请号：US13438658

申请日：2012-04-03

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G01R31/3177 ,  G06F11/25

CPC classification number: G01R31/318563 ,  G01R31/318536

Abstract: An integrated circuit comprising (i) a plurality of portions, each portion including test control circuitry; and (ii) at least one test input arranged to receive test signals, the circuit having a test mode in which one or more of the plurality of portions are testable, wherein the circuit has a reset mode which has priority over the test mode.

Abstract translation: 一种集成电路，包括（i）多个部分，每个部分包括测试控制电路; 以及（ii）布置成接收测试信号的至少一个测试输入，所述电路具有其中所述多个部分中的一个或多个部分是可测试的测试模式，其中所述电路具有优于所述测试模式的重置模式。

公开(公告)号：US08046647B2

公开(公告)日：2011-10-25

申请号：US12657642

申请日：2010-01-25

Applicant: Robert Warren

Inventor： Robert Warren

IPC: G01R31/28 ,  G11C29/00 ,  G01R31/26

CPC classification number: G01R31/318555 ,  G01R31/318536 ,  G01R31/318552 ,  G01R31/318558 ,  G01R31/318563 ,  G01R31/3187

Abstract: An integrated circuit comprising: at least one test input for receiving test data; test control circuitry between the at least one test input and circuitry to be tested; wherein the test data is clocked in on a rising clock edge and a falling clock edge.

Abstract translation: 一种集成电路，包括：用于接收测试数据的至少一个测试输入; 所述至少一个测试输入和要测试的电路之间的测试控制电路; 其中测试数据在上升时钟沿和下降时钟沿被计时。

公开(公告)号：US08042157B2

公开(公告)日：2011-10-18

申请号：US11465535

申请日：2006-08-18

Applicant: Peter Bennett ,  Andrew Dellow

Inventor： Peter Bennett ,  Andrew Dellow

IPC: H04L29/00

CPC classification number: H04N21/443 ,  H04H60/23 ,  H04H60/80

Abstract: A filter is arranged to selectively block or allow a data access command from an initiator according to whether the initiator is secure or insecure and whether a data source or destination being accessed is privileged or unprivileged. The data access command contains an identification of the initiator from which the data access command originated and an identification of the data source or destination being accessed. The security filter compares the initiator identification and data source or destination identification contained within the data access command with a list of those initiators defined as secure and a list of those data sources or destinations which are defined as unprivileged. The filter then blocks or allows the data access command signal according to a set of rules.

Abstract translation: 布置过滤器以根据启动器是安全的还是不安全的以及被访问的数据源或目的地是特权还是非特权来选择性地阻止或允许来自发起者的数据访问命令。 数据访问命令包含发起数据访问命令的启动器的标识以及所访问的数据源或目的地的标识。 安全过滤器将包含在数据访问命令中的启动器标识和数据源或目的地标识与定义为安全的那些启动器的列表以及被定义为无特权的那些数据源或目的地的列表进行比较。 然后，滤波器根据一组规则阻止或允许数据访问命令信号。

公开(公告)号：US07890628B2

公开(公告)日：2011-02-15

申请号：US10913793

申请日：2004-08-06

Applicant: Julian Marcus Wilson ,  Steven Nicholas Haydock ,  Brendan O'Connor

Inventor： Julian Marcus Wilson ,  Steven Nicholas Haydock ,  Brendan O'Connor

IPC: G06F15/173

CPC classification number: H04L67/16 ,  H04L67/02 ,  H04L67/10 ,  H04L67/12 ,  H04L69/329

Abstract: A method and apparatus are provided for controlling services provided at a first electronic device at a second electronic device. A plurality of electronic devices connected to a network provide services in the form of providing data to the network, or allowing the data to be manipulated. Each service is represented as a manipulable data object created at the device providing the service. Each object contains sufficient information to allow the service the object represents to be controlled. The objects are transmitted over the network and are stored in an object list maintained by a master device. Any compatible device may then retrieve an object from the object list and use the information contained in it to fully control the service.

Abstract translation: 提供了一种用于控制在第二电子设备处提供在第一电子设备处的服务的方法和装置。 连接到网络的多个电子设备以向网络提供数据或允许数据被操纵的形式提供服务。 每个服务都表示为在提供服务的设备上创建的可操纵的数据对象。 每个对象包含足够的信息来允许对象表示的服务被控制。 对象通过网络传输并存储在由主设备维护的对象列表中。 任何兼容设备然后可以从对象列表中检索对象，并使用其中包含的信息来完全控制服务。

公开(公告)号：US20100290466A1

公开(公告)日：2010-11-18

申请号：US12781118

申请日：2010-05-17

Applicant: Matt Morris

Inventor： Matt Morris

IPC: H04L12/56

CPC classification number: H04L49/25 ,  H04L49/103

Abstract: The routing of data streams is discussed, and particularly routing one or more incoming streams to one or more output destination ports. The ability to merge incoming streams is discussed so that several low bit rate input packet streams can be merged into a higher bit rate output stream. An assignment data structure identifies for each input stream the or each destination to which it is to be routed, and a packet allocation data structure holds information about the packets and information about the destination of the packets to allow a memory holding the packets to be controlled accordingly.

Abstract translation: 讨论数据流的路由，特别是将一个或多个输入流路由到一个或多个输出目的地端口。 讨论合并输入流的能力，使得几个低比特率输入分组流可以被合并到更高比特率的输出流中。 分配数据结构为每个输入流标识其要路由的每个目的地，并且分组分配数据结构保存关于分组的信息和关于分组的目的地的信息，以允许控制分组的存储器 相应地。

公开(公告)号：US07793261B1

公开(公告)日：2010-09-07

申请号：US09411792

申请日：1999-10-01

Applicant: David Alan Edwards ,  Margaret Rose Gearty ,  Glenn A. Farrall ,  Atsushi Hasegawa ,  Anthony Willis Rich

Inventor： David Alan Edwards ,  Margaret Rose Gearty ,  Glenn A. Farrall ,  Atsushi Hasegawa ,  Anthony Willis Rich

IPC: G06F9/44

CPC classification number: G06F11/3636 ,  G06F11/261 ,  G06F11/3656

Abstract: An microcomputer is provided including a processor and a debug circuit including a dedicated link which transfers information between the processor and debug circuit to support debugging operations. In one aspect, the processor provides program counter information, which is stored in a memory-mapped register of the debug circuit. The program counter information may be a value of the processor program counter at a writeback stage of a processor pipeline. Also, trace information including message information is transferred in a non-intrusive manner over the dedicated link. In one aspect, the microcomputer is implemented as a single integrated circuit.

Abstract translation: 提供一种包括处理器和调试电路的微计算机，该调试电路包括专用链路，该专用链路在处理器和调试电路之间传送信息以支持调试操作 在一个方面，处理器提供存储在调试电路的存储器映射寄存器中的程序计数器信息。 程序计数器信息可以是处理器管线的回写阶段处理器程序计数器的值。 此外，包括消息信息的跟踪信息通过专用链路以非侵入方式传送。 一方面，微型计算机被实现为单个集成电路。

公开(公告)号：US20100115498A1

公开(公告)日：2010-05-06

申请号：US12686987

申请日：2010-01-13

Applicant: Richard Shann ,  Marian MacCormack

Inventor： Richard Shann ,  Marian MacCormack

IPC: G06F9/45 ,  G06F9/44

CPC classification number: G06F8/447 ,  G06F8/47

Abstract: A system for providing an assembler for a microprocessor has a file which contains data describing the instruction set of the microprocessor. A translation device for translating into machine language accesses the instruction set descriptors to constrain the machine code output of the assembler to conform to the architecture of the instruction set.

Abstract translation: 用于为微处理器提供汇编器的系统具有包含描述微处理器的指令集的数据的文件。 用于转换为机器语言的翻译装置访问指令集描述符以约束汇编器的机器代码输出以符合指令集的架构。

公开(公告)号：US07624442B2

公开(公告)日：2009-11-24

申请号：US10817148

申请日：2004-04-02

Applicant: Andrew Dellow ,  Peter Bennett

Inventor： Andrew Dellow ,  Peter Bennett

IPC: G06F11/00

CPC classification number: G06F21/72 ,  G06F12/1441 ,  G06F21/57 ,  G06F2221/2105

Abstract: A semiconductor integrated circuit includes a processor for executing application code from a memory and a verifier processor arranged to receive the application code via the same internal bus as the processor. The verifier processor performs a verification function to check that the application code is authentic. The verifier processor runs autonomously and cannot be spoofed as it receives the application code via the same internal bus as the main processor. An additional instruction monitor checks the code instructions from the CPU and also impairs the operation of the circuit unless the address of code requested is in a given range. The code is in the form of a linked list and the range is derived as a linked list table during a first check.

Abstract translation: 半导体集成电路包括用于从存储器执行应用代码的处理器和被布置为经由与处理器相同的内部总线接收应用代码的验证器处理器。 验证者处理器执行验证功能以检查应用代码是否可信。 验证者处理器自动运行，并且不能通过与主处理器相同的内部总线接收应用代码而被欺骗。 附加的指令监视器检查来自CPU的代码指令，并且还损害电路的操作，除非所请求的代码的地址在给定的范围内。 代码是链表的形式，并且在第一次检查期间将该范围派生为链表。