公开(公告)号：US20230326994A1

公开(公告)日：2023-10-12

申请号：US18189621

申请日：2023-03-24

申请人： Samsung Electronics Co., Ltd.

发明人： Sungil Park ,  Jae Hyun Park

IPC分类号： H01L29/66 ,  H01L27/082 ,  H01L29/08 ,  H01L29/10 ,  H01L27/102

CPC分类号： H01L29/66303 ,  H01L27/082 ,  H01L27/1022 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/0804

摘要： A semiconductor device includes a semiconductor body having first and second surfaces opposite to each other. The semiconductor body includes a first well region having a first conductivity type, second and third well regions spaced apart from each other in a first direction with the first well region interposed therebetween and having a second conductivity type, first doped regions spaced apart from each other in a second direction intersecting the first direction in the first well region, a second doped region, which is adjacent to the second well region and has the second conductivity type, and a third doped region, which is adjacent to the third well region and has the second conductivity type. The second surface of the semiconductor body includes bottom surfaces of the first to third well regions, the plurality of first doped regions, the second doped region, and the third doped region.

公开(公告)号：US09722059B2

公开(公告)日：2017-08-01

申请号：US14832959

申请日：2015-08-21

申请人： INFINEON TECHNOLOGIES AG

发明人： Alim Karmous

IPC分类号： H01L29/739 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/66 ,  H01L29/417

CPC分类号： H01L29/7395 ,  H01L29/0696 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1095 ,  H01L29/41708 ,  H01L29/45 ,  H01L29/47 ,  H01L29/66295 ,  H01L29/66303 ,  H01L29/6634 ,  H01L29/66348 ,  H01L29/7393 ,  H01L29/7397

摘要： There are disclosed herein various implementations of a latch-up free power transistor. Such a device includes an insulated gate situated adjacent to a conduction channel in the power transistor, an emitter electrode in direct physical contact with the conduction channel, and a collector electrode in electrical contact with the conduction channel. The power transistor also includes an emitter layer in contact with a surface of a semiconductor substrate adjacent the conduction channel.

公开(公告)号：US20170125295A1

公开(公告)日：2017-05-04

申请号：US15278332

申请日：2016-09-28

申请人： Renesas Electronics Corporation

发明人： Shinichi MAEDA

IPC分类号： H01L21/8222 ,  H01L21/324 ,  H01L27/082

CPC分类号： H01L21/8222 ,  H01L21/324 ,  H01L27/082 ,  H01L29/0813 ,  H01L29/66303 ,  H01L29/732

摘要： It is prevented that when a predetermined number of semiconductor chips having transistors are manufactured from one semiconductor wafer, manufacturing cost of a semiconductor device is increased due to excess semiconductor chips manufactured from the semiconductor wafer. A first bipolar transistor including a first emitter region having a first area is formed in a first chip formation region in an exposure region that can be exposed by one exposure step, and a second bipolar transistor including a second emitter region having a second area different from the first area is formed in a second chip formation region in the exposure region.

公开(公告)号：US09466688B2

公开(公告)日：2016-10-11

申请号：US15089857

申请日：2016-04-04

申请人： NXP B.V.

发明人： Soenke Habenicht ,  Detlef Oelgeschlager ,  Olrik Schumacher ,  Stefan Bengt Berglund

IPC分类号： H01L21/8249 ,  H01L29/66 ,  H01L29/08 ,  H01L29/10 ,  H01L29/417

CPC分类号： H01L29/66303 ,  H01L29/0692 ,  H01L29/0813 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/66295 ,  H01L29/732

摘要： The present invention provides a semiconductor with a multilayered contact structure. The multilayered structure includes a metal contact placed on an active region of a semiconductor and a metal contact extension placed on the metal contact.

公开(公告)号：US20120248575A1

公开(公告)日：2012-10-04

申请号：US13512366

申请日：2009-12-21

申请人： Soenke Habenicht ,  Detief Oelgeschlaeger ,  Olrik Schumacher ,  Stefan Bengt Berglund

发明人： Soenke Habenicht ,  Detief Oelgeschlaeger ,  Olrik Schumacher ,  Stefan Bengt Berglund

IPC分类号： H01L29/73 ,  H01L21/50 ,  H01L21/331

CPC分类号： H01L29/66303 ,  H01L29/0692 ,  H01L29/0813 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/66295 ,  H01L29/732

摘要： The present invention provides a semiconductor with a multilayered contact structure. The multilayered structure includes a metal contact placed on an active region of a semiconductor and a metal contact extension placed on the metal contact.

摘要翻译： 本发明提供具有多层接触结构的半导体。 多层结构包括设置在半导体的有源区域上的金属接触件和放置在金属接触件上的金属接触延伸部分。

公开(公告)号：US5661079A

公开(公告)日：1997-08-26

申请号：US490487

申请日：1995-06-14

申请人： Hartmut Harmel ,  Uwe Kellner-Werdehausen

发明人： Hartmut Harmel ,  Uwe Kellner-Werdehausen

IPC分类号： H01L21/3205 ,  H01L21/331 ,  H01L21/28

CPC分类号： H01L29/66303 ,  H01L21/32051 ,  Y10S438/958

摘要： The invention relates to a method for contacting SIPOS-passivated semiconductor zones on a semiconductor body, where the removal of the oxide layer from the wafer surface takes place at the same time as the oxide etching before SIPOS passivation. The double-layered SIPOS passivation consists here of a N-SIPOS layer and a O-SIPOS layer. For contact opening, only the N-SIPOS layer is removed by wet chemical etching. By annealing the previously vaporized and structured metallization, a good contact results which can also carry a high current. The process according to the invention involves a simple sequence of operations and an underetching of the passivation layers and the disadvantages resulting from this are reliably avoided.

摘要翻译： 本发明涉及一种用于接触半导体主体上的SIPOS钝化半导体区域的方法，其中与SIPOS钝化之前的氧化物蚀刻同时从晶片表面去除氧化物层。 双层SIPOS钝化包括N-SIPOS层和O-SIPOS层。 对于接触开口，仅通过湿化学蚀刻除去N-SIPOS层。 通过对先前蒸发和结构化的金属化进行退火，可以产生良好的接触，其也可承载高电流。 根据本发明的方法涉及简单的操作顺序和钝化层的不起弧，并且由此可靠地避免了由此产生的缺点。

公开(公告)号：US5405789A

公开(公告)日：1995-04-11

申请号：US141888

申请日：1993-10-22

申请人： Ronald Dekker ,  Henricus G. R. Maas ,  Armand Pruijmboom ,  Wilhelmus T. A. J. Van Den Einden

发明人： Ronald Dekker ,  Henricus G. R. Maas ,  Armand Pruijmboom ,  Wilhelmus T. A. J. Van Den Einden

IPC分类号： H01L21/28 ,  H01L21/331 ,  H01L21/335 ,  H01L21/336 ,  H01L21/8249 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/66303 ,  H01L21/28 ,  H01L21/8249 ,  H01L29/66416

摘要： A method of manufacturing a semiconductor device with a semiconductor element which includes a semiconductor zone (19) situated below an electrode (18) and adjoining a surface (5) of a semiconductor body (1), which semiconductor zone substantially does not project outside the electrode (18) in lateral direction. The electrode (18) is here formed on the surface (5) of the semiconductor body (1), after which semiconductor material adjoining the surface (5) and not covered by the electrode (18) is removed by an etching treatment, whereby the position of the semiconductor zone (19) below the electrode (18) is defined. Before the electrode (18) is formed, a surface zone (16) adjoining the surface (5) is formed in the semiconductor body (1) with a depth and a doping such as are desired for the semiconductor zone (19) to be formed below the electrode (18), after which the electrode (18) is formed on this surface zone and, during the etching treatment, the portion of the surface zone (16) not covered by the electrode (18) is etched away through its entire thickness. Conducting materials such as aluminium or aluminium alloys may be used for the electrode (18), i.e. materials which are not resistant to temperatures necessary for forming semiconductor zones through diffusion.

摘要翻译： 一种制造具有半导体元件的半导体器件的方法，该半导体元件包括位于电极（18）下方并邻接半导体本体（1）的表面（5）的半导体区（19），该半导体区基本上不会突出在半导体本体 电极（18）。 此时，电极（18）形成在半导体本体（1）的表面（5）上，然后通过蚀刻处理去除邻接表面（5）并且未被电极（18）覆盖的半导体材料，由此， 限定电极（18）下方的半导体区域（19）的位置。 在形成电极（18）之前，在半导体本体（1）中形成与表面（5）相邻的表面区域（16），以形成半导体区域（19）所需的深度和掺杂 在电极（18）的下方，之后在该表面区域上形成电极（18），并且在蚀刻处理期间，未被电极（18）覆盖的表面区域（16）的部分通过其整个 厚度。 可以使用诸如铝或铝合金的导电材料用于电极（18），即不耐受通过扩散形成半导体区域所需的温度的材料。

公开(公告)号：US5376563A

公开(公告)日：1994-12-27

申请号：US210267

申请日：1994-03-18

申请人： William P. Imhauser

发明人： William P. Imhauser

IPC分类号： H01L21/331 ,  H01L29/732 ,  H01L21/265

CPC分类号： H01L29/66303 ,  H01L29/732 ,  Y10S148/01

摘要： Using a silicon etched technique to remove an implanted base and emitter surrounding emitter-base islands, a "mesa" emitter structure can be formed. Using the structure, a self aligned P+ can be formed around emitter-base islands.

摘要翻译： 使用硅蚀刻技术去除围绕发射极 - 基极岛的注入的基极和发射极，可以形成“台面”发射极结构。 使用该结构，可以在发射极 - 基岛周围形成自对准P +。

公开(公告)号：US4725874A

公开(公告)日：1988-02-16

申请号：US919554

申请日：1986-10-16

申请人： Hirotomo Ooga ,  Hiromi Sakurai

发明人： Hirotomo Ooga ,  Hiromi Sakurai

IPC分类号： H01L29/73 ,  H01L21/20 ,  H01L21/331 ,  H01L27/12 ,  H01L29/10 ,  H01L27/02

CPC分类号： H01L29/66287 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/02647 ,  H01L29/1004 ,  H01L29/66303 ,  Y10S438/965 ,  Y10S438/969

摘要： An N.sup.- silicon layer is epitaxially grown on an oxide film with predetermined openings disposed on one main face of an N.sup.+ silicon substrate to form monocrystalline portions on the openings and polycrystalline portions on the oxide film. Ion implantation and thermal annealing is used to convert the polycrystalline portions to P.sup.+ external base regions and form P.sup.+ internal base regions in the monocrystalline portions. Arsenic ions are selectively implanted into the internal base regions to form N.sup.+ emitter regions. Then, base and emitter electrodes are formed on the external base and emitter regions so as to be electrically insulated from one another by an oxide film and a collector electrode is formed on the other main face of the substrate.

摘要翻译： 在具有设置在N +硅衬底的一个主面上的预定开口的氧化物膜上外延生长N-硅层，以在氧化物膜上的开口和多晶部分上形成单晶部分。 离子注入和热退火用于将多晶部分转换为P +外部基极区域并在单晶部分中形成P +内部基极区域。 砷离子被选择性地注入内部碱性区域以形成N +发射极区域。 然后，在外部基极和发射极区域上形成基极和发射极，以便通过氧化膜彼此电绝缘，并且在基板的另一主面上形成集电极。

公开(公告)号：US3756873A

公开(公告)日：1973-09-04

申请号：US3756873D

申请日：1970-03-12

申请人： TELEFUNKEN PATENT

发明人： KAISER R

IPC分类号： H01L21/331 ,  H01L29/00 ,  H01L29/08 ,  H01L7/34

CPC分类号： H01L29/0821 ,  H01L29/00 ,  H01L29/66295 ,  H01L29/66303 ,  Y10S148/04

摘要： A TRANSISTOR HAVING AN EMITTER ZONE AND A COLLECTOR ZONE SEPARATED BY A BASE ZONE, AND A METHOD OF MAKING THE SAME. THE REGION OF THE COLLECTOR ZONE ADJACENT TO THE BASE ZONE AND OPPOSITE THE EMITTER ZONE IS OF LOWER RESISTANCE THAN THE REMAINDER OF THE COLLECTOR ZONE. THE METHOD OF FORMING THE TRANSISTOR ENTAILS OPENING A DIFFUSION WINDOW OF THE SIZE AND LOCATION OF AN EMITTER DIFFUSION WINDOW IN A DIFFUSION MASKING LAYER FORMED ON THE SURFACE OF A SEMICONDUCTOR BODY OF A FIRST CONDUCTIVITY TYPE, AND FORMING A LOW-OHMIC REGION OF THE FIRST CONDUCTIVITY WITHIN THE SEMICONDUCTOR BODY BY THE DIFFUSION OF AN IMPURITY. THE BASE DIFFUSION WINDOW IS THEN OPENED AND THE BASE ZONE FORMED

BY DIFFUSION SO THAT THE BASE ZONE EXTENDS TO A LESSER DEPTH FROM THE SURFACE OF THE SEMICONDUCTOR BODY THAN THE LOW OHMIC REGION, AND FINALLY THE EMITTER DIFFUSION WINDOW IS OPENED AT THE LOCATION AND OF THE SIZE OF THE FIRST OPENED DIFFUSION WINDOW AND AN EMITTER ZONE IS FORMED BY DIFFUSION IN THE BASE ZONE.