公开(公告)号：US12009951B2

公开(公告)日：2024-06-11

申请号：US17186897

申请日：2021-02-26

申请人： Marvell Asia Pte Ltd.

发明人： Todd Rope ,  Ilya Lyubomirsky ,  Whay Sing Lee ,  Arash Farhoodfar

IPC分类号： H04L25/03 ,  G06N20/00 ,  H04B10/079

CPC分类号： H04L25/03261 ,  G06N20/00 ,  H04B10/0795

摘要： Embodiments address optimization of an electrical interface between an optical host device and an optical module device at installation time. Certain methods try each entry in a set of Finite Impulse Response (FIR) filter settings at the host transmitter, while asking the module to measure the signal integrity for each. The module will then provide an indication of which entry was the best choice for signal integrity in the current hardware configuration. Note that for the module to host electrical interface, this same technique can be used in reverse, whereby the host asks the module to configure its transmitting FIR filter, and the host records and keeps track of which filter setting is the best, and then configures the module with that filter setting. In both cases, for modules supporting CMIS (Common Management Interface Specification) for module configuration and control, methods are provided.

公开(公告)号：US11924132B2

公开(公告)日：2024-03-05

申请号：US17959012

申请日：2022-10-03

申请人： Apple Inc.

发明人： Zhibin Yu ,  Michael Ruder ,  Holger Neuhaus ,  Yeong-Sun Hwang ,  Bertram Gunzelmann

IPC分类号： H04W72/04 ,  H04B7/06 ,  H04B7/08 ,  H04L5/00 ,  H04L25/03

CPC分类号： H04L5/0048 ,  H04B7/0814 ,  H04B7/088 ,  H04L25/03261

摘要： A communication device comprises a receiver including at least two receive antennas and configured to receive at least one reference signal of a plurality of reference signals, each reference signal being transmitted from at least one base station at a predefined reference signal transmission time; a controller configured to switch between at least two receive configurations of the at least two antennas during a reception period of the at least one reference signal; and a signal quality determiner configured to determine a parameter indicative of a first signal quality of the received reference signal for each receive configuration.

公开(公告)号：US20160218899A1

公开(公告)日：2016-07-28

申请号：US14686289

申请日：2015-04-14

申请人： Texas Instruments Incorporated

发明人： Reza Hoshyar ,  Kevin Zheng ,  Nirmal Warke ,  Wenting Zhou ,  Ali Kiaei ,  Ahmad Bahai

IPC分类号： H04L27/01 ,  H04L7/033 ,  H04L27/34 ,  H04L25/03

CPC分类号： H04L25/03057 ,  H04L7/0004 ,  H04L7/0016 ,  H04L7/0087 ,  H04L7/033 ,  H04L7/0331 ,  H04L7/042 ,  H04L25/03019 ,  H04L25/03261 ,  H04L25/03267 ,  H04L25/03885 ,  H04L27/01 ,  H04L27/34 ,  H04L2025/03363 ,  H04L2025/03484 ,  H04L2025/0349 ,  H04L2025/03636

摘要： A Continuous Time Linear Equalizer (CTLE) and a method of operating a CTLE in a receiver for a Pulse Amplitude Modulation (PAM) signal are disclosed. The method includes initiating equalization using an initial equalization setting that is optimized to meet a first objective and responsive to a determination, shifting to a final equalization setting that is optimized to meet a second objective.

摘要翻译： 公开了一种连续时间线性均衡器（CTLE）和用于脉冲幅度调制（PAM）信号的接收机中操作CTLE的方法。 该方法包括使用初始均衡设置启动均衡，该初始均衡设置被优化以满足第一目标并且响应于确定，转移到被优化以满足第二目标的最终均衡设置。

公开(公告)号：US20160020928A1

公开(公告)日：2016-01-21

申请号：US14532617

申请日：2014-11-04

申请人： Goodrich Corporation

发明人： Efrem E. Ayichew ,  Michael Abbott

IPC分类号： H04L25/03 ,  B64C25/42

CPC分类号： H04L25/03261 ,  B60T8/1703 ,  B60T13/741 ,  B64C25/42 ,  B64C25/44 ,  B64C25/46

摘要： The present disclosure relates to control actuation smoothing, and more particularly, to a control actuation smoothing system that smoothes brake actuation. The smoothing may be determined in response to a filter. In various embodiments, the smoothing may enhance brake component performance.

摘要翻译： 本公开涉及控制致动平滑，更具体地，涉及平滑制动器致动的控制致动平滑系统。 可以响应于过滤器来确定平滑。 在各种实施例中，平滑可以增强制动部件的性能。

公开(公告)号：US20150171886A1

公开(公告)日：2015-06-18

申请号：US14105215

申请日：2013-12-13

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

发明人： Martin KINYUA

IPC分类号： H03M1/66 ,  H04L25/03

CPC分类号： H03M1/661 ,  H03M1/747 ,  H03M3/414 ,  H03M3/50 ,  H03M3/504 ,  H04L25/03261 ,  H04L2025/03363

摘要： A system and method is disclosed for a digital to analog converter which includes an interpolation filter to up-sample a digital signal, a cascaded digital pulse width modulation noise shaper having multiple stages to suppress in-band quantization errors due to digital pulse width modulation and truncation errors, and a hybrid finite impulse response filter/digital to analog converter coupled to a reconstruction filter which outputs the analog signal. The cascaded noise shaper stages each operate using the same quantization error signal.

摘要翻译： 公开了一种用于数模转换器的系统和方法，该数模转换器包括用于对数字信号进行采样的内插滤波器，具有多级的级联数字脉宽调制噪声整形器，用于抑制由数字脉宽调制引起的带内量化误差， 截断误差，以及耦合到输出模拟信号的重构滤波器的混合有限脉冲响应滤波器/数模转换器。 级联噪声整形器级使用相同的量化误差信号进行操作。

公开(公告)号：US07551668B2

公开(公告)日：2009-06-23

申请号：US11084786

申请日：2005-03-21

申请人： Satoru Higashino ,  Yoshiyuki Kajiwara

发明人： Satoru Higashino ,  Yoshiyuki Kajiwara

IPC分类号： H03H7/30

CPC分类号： H04L25/03261 ,  H04L25/03171 ,  H04L25/03222 ,  H04L25/03267 ,  H04L25/03299 ,  H04L2027/003 ,  H04L2027/0053 ,  H04L2027/0085

摘要： An adaptive equalizing apparatus that can positively remove the leading Inter Symbol Interference (ISI), make a maximum-likelihood decoding and an optimum equalization on the basis of the result of the maximum-likelihood decoding with consideration being given to the asymmetry of an input waveform. The adaptive equalizing apparatus includes a feedforward filter, a maximum-likelihood decoder, a feedback filter, a delay unit, and a subtracter. In the feedback filter, the tap factor is controlled on the basis of the binary signal generated by the maximum-likelihood decoding to generate a distortion of a partial response after the leading edge of the binary signal and an ISI response after the trailing edge. In the feedforward filter, the tap factor for the signal supplied from the subtracter is controlled to be a partial response.

摘要翻译： 考虑到输入波形的不对称性，可以肯定地去除领先的符号间干扰（ISI）的自适应均衡装置基于最大似然解码的结果进行最大似然解码和最优均衡 。 自适应均衡装置包括前馈滤波器，最大似然解码器，反馈滤波器，延迟单元和减法器。 在反馈滤波器中，基于由最大似然解码产生的二进制信号来控制抽头因子，以在二进制信号的前沿和后沿之后的ISI响应之后产生部分响应的失真。 在前馈滤波器中，从减法器提供的信号的抽头因子被控制为部分响应。

公开(公告)号：US07248849B1

公开(公告)日：2007-07-24

申请号：US10454421

申请日：2003-06-03

申请人： Sirikiat L. Ariyavisitakul ,  Manoneet Singh

发明人： Sirikiat L. Ariyavisitakul ,  Manoneet Singh

IPC分类号： H04B1/10

CPC分类号： H04L25/022 ,  H04L25/03261 ,  H04L25/03292

摘要： A prefilter is trained as follows. The frequency response B of a conditioned channel is determined without reference to the prefilter, and the frequency response W of the prefilter is computed from the frequency response B of the conditioned channel.

摘要翻译： 预过滤器的培训如下。 在不参考预过滤器的情况下确定经调节的通道的频率响应B，并且根据经调节的通道的频率响应B来计算预过滤器的频率响应W.

公开(公告)号：US20070140330A1

公开(公告)日：2007-06-21

申请号：US11608998

申请日：2006-12-11

申请人： Steve Allpress ,  Quinn Li

发明人： Steve Allpress ,  Quinn Li

IPC分类号： H03H7/30 ,  H04B1/10 ,  H03H7/40

CPC分类号： H04L25/03261 ,  H04L25/03057 ,  H04L25/03076 ,  H04L25/03146 ,  H04L25/03171 ,  H04L2025/03401 ,  H04L2025/0349 ,  H04L2025/0356 ,  H04L2025/03796

摘要： An apparatus and method for implementing an equalizer which (1) combines the benefits of a decision feedback equalizer (DFE) with a maximum-a-posterori (MAP) equalizer (or a maximum likelihood sequence estimator, MLSE) (2) performs equalization in a time-forward or time-reversed manner based on the channel being minimum-phase or maximum-phase to provide an equalization device with significantly lower complexity than a full-state MAP device, but which still provides improved performance over a conventional DFE. The equalizer architecture includes two DFE-like structures, followed by a MAP equalizer. The first DFE forms tentative symbol decisions. The second DFE is used thereafter to truncate the channel response to a desired memory of L1 symbols, which is less than the total delay spread of L symbols of the channel. The MAP equalizer operates over a channel with memory of L1 symbols (where L1

摘要翻译： （1）将判决反馈均衡器（DFE）与最大后缀（MAP）均衡器（或最大似然序列估计器，MLSE）（2）的优点相结合的均衡器的装置和方法（2）执行均衡 基于信道是最小相位或最大相位的时间前向或时间反转方式来提供具有比全状态MAP设备显着更低的复杂度的均衡设备，但仍然提供比常规DFE更好的性能。 均衡器架构包括两个类似DFE的结构，其次是MAP均衡器。 第一个DFE形成暂定的符号决定。 此后使用第二DFE来截断对于L1 L1符号的期望存储器的信道响应，其小于信道的L个符号的总延迟扩展。 MAP均衡器在具有L 1 1符号（其中L 1> L =）的存储器的信道上操作，因此均衡器的总体复杂度显着降低。

公开(公告)号：US07212595B2

公开(公告)日：2007-05-01

申请号：US10408364

申请日：2003-04-08

申请人： Tai-Lai Tung ,  Mike Tu

发明人： Tai-Lai Tung ,  Mike Tu

IPC分类号： H04B1/10

CPC分类号： H04L25/03261 ,  H04L2025/03414 ,  H04L2025/03445 ,  H04L2025/03605

摘要： The present invention provides a system and method for implementing a new TEQ training approach that trains TEQ coefficients by exploiting both time-domain and frequency-domain information. An advantage of this technique is that it reduces memory usage due to the training process. In addition, the complexity of the training process is simplified, and the associated computational work is reduced. The reduction of memory usage and computational work in turn may lead to cost savings, power consumption savings and other advantages.

摘要翻译： 本发明提供一种用于实现新的TEQ训练方法的系统和方法，其通过利用时域和频域信息来训练TEQ系数。 该技术的优点在于它减少了由于训练过程而导致的内存使用。 另外，简化了训练过程的复杂性，减少了相关的计算工作。 内存使用和计算工作的减少又可能导致成本节省，节省功耗以及其他优点。

公开(公告)号：US20050232133A1

公开(公告)日：2005-10-20

申请号：US11097979

申请日：2005-04-01

申请人： Wladimir Bocquet ,  Yoshinori Tanaka

发明人： Wladimir Bocquet ,  Yoshinori Tanaka

IPC分类号： H04B1/707 ,  H04B1/7103 ,  H04J11/00 ,  H04L25/03 ,  H04L27/26

CPC分类号： H04L27/265 ,  H04L5/0007 ,  H04L25/0216 ,  H04L25/023 ,  H04L25/03159 ,  H04L25/03261 ,  H04L27/2605 ,  H04L2025/03414 ,  H04L2025/03522 ,  H04L2025/03585

摘要： A multi-carrier receiver which dispenses with a guard interval and avoids an influence of an intersymbol interference (ISI) based on the height of the guard interval. This multi-carrier receiver has a serial/parallel converter for receiving a multi-carrier signal to convert it into a parallel signal, a Fourier transformer for selecting a multi-carrier signal over a section longer than one symbol of the received multi-carrier signal from an output of the serial/parallel converter to subject the selected multi-carrier signal to discrete Fourier transform, a channel compensator for subjecting the Fourier transform signal to channel equalization, a matrix conveter for contracting the dimension of the signal of channel equalized signal down to the dimension of the received multi-carrier signal, a parallel/serial converter for converting the output of the matrix converter into a serial signal, and a demodulator for matching the output of the parallel/serial converter with the modulator on a transmitter side, and a decoder for matching it with an encoder.

摘要翻译： 一种多载波接收机，其基于保护间隔的高度而省略了保护间隔并避免了符号间干扰（ISI）的影响。 该多载波接收机具有用于接收多载波信号以将其转换为并行信号的串行/并行转换器，傅立叶变换器，用于在比接收的多载波信号的一个符号长的部分上选择多载波信号 从串行/并行转换器的输出将所选择的多载波信号进行离散付里叶变换，用于对傅立叶变换信号进行信道均衡的信道补偿器，用于将信道均衡信号的信号尺寸缩小的矩阵振荡器 对于所接收的多载波信号的维度，将矩阵转换器的输出转换为串行信号的并行/串行转换器，以及用于使并行/串行转换器的输出与发射机侧的调制器相匹配的解调器， 以及用于与编码器匹配的解码器。