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公开(公告)号：US20220299448A1
公开(公告)日：2022-09-22
申请号：US17317906
申请日：2021-05-12
发明人： Dian Han Liu , MAOHUA REN , Yuan-Chi Pai , WEN YI TAN
摘要： A method for aligning to a pattern on a wafer is disclosed. The method includes the steps of obtaining a first inline image from a first sample wafer, obtaining a first contour pattern of an alignment mark pattern from the first inline image, using the first contour pattern to generate a first synthetic image in black and white pixels, using the first synthetic image as a reference to recognize the alignment mark pattern on a tested wafer, and aligning to a tested pattern on the tested wafer according to a position of the alignment mark pattern on the tested wafer and a coordinate information.
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公开(公告)号：US11387150B2
公开(公告)日：2022-07-12
申请号：US17129848
申请日：2020-12-21
发明人： Hui Min Chen , Song Gu , Kai Ping Huang , Wen Yi Tan
IPC分类号： H01L21/8238 , H01L21/266 , H01L21/762
摘要： A method of decreasing height differences of STIs includes providing a substrate comprising a peripheral circuit region. The peripheral circuit region includes a P-type transistor region and an N-type transistor region. A first STI and a third STI are respectively disposed within the N-type transistor region and the P-type transistor region. Later, a first mask is formed to cover the N-type transistor region. Then, an N-type well is formed in the P-type transistor region and part of the third STI is removed by taking the first mask as a mask. Next, the first mask is removed. After that, a second mask is formed to cover the P-type transistor region. Subsequently, a P-type well is formed in the N-type transistor region and part of the first STI is removed by taking the second mask as a mask. Finally, the second mask is removed.
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公开(公告)号：US20220139778A1
公开(公告)日：2022-05-05
申请号：US17109108
申请日：2020-12-01
发明人： XIONGWU HE , WEIGUO XU , Yuan-Chi Pai , WEN YI TAN
IPC分类号： H01L21/768 , H01L21/66 , H01L21/311 , G03F7/20 , G03F1/42 , G03F1/86
摘要： A manufacturing method of a contact structure includes the following steps. A substrate is provided, and the substrate includes a first region and a second region. A dielectric layer is formed on the substrate. A photoresist layer is formed on the dielectric layer. An exposure process is performed. The exposure process includes first exposure steps and second exposure steps. Each of the first exposure steps is performed to a part of the first region of the substrate. Each of the second exposure steps is performed to a part of the second region of the substrate. Each of the second exposure steps is performed with a first overlay shift by a first predetermined distance. A develop process is performed for forming openings in the photoresist layer.
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公开(公告)号：US20220068723A1
公开(公告)日：2022-03-03
申请号：US17026319
申请日：2020-09-21
发明人： TAO HU , Xiao Dong Shi , JINJIAN OUYANG , WEN YI TAN
IPC分类号： H01L21/8238 , H01L29/66
摘要： A method for forming a semiconductor device is disclosed. A semiconductor substrate having thereon an NMOS region, a PMOS region, and a non-silicide region is provided. An NMOS transistor is formed within the NMOS region and a PMOS transistor is formed within the PMOS region. A stress memorization technique (SMT) layer covering the NMOS region, the PMOS region, and the non-silicide region is formed. The SMT layer is removed from the PMOS region. A stress is transferred from the SMT layer into an N-channel of the NMOS transistor. The SMT layer is removed from the NMOS region, while leaving the SMT layer in the non-silicide region intact. A self-aligned silicidation (SAC) process is performed to form a salicide layer in the NMOS region and the PMOS region.
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公开(公告)号：US20220056582A1
公开(公告)日：2022-02-24
申请号：US17516727
申请日：2021-11-02
发明人： Min-Fu Lee
IPC分类号： C23C16/458 , H01L21/687 , C23C16/46 , C23C16/50
摘要： A chamber for processing deposition on a wafer includes a wafer holder having a central surface region for placing a wafer and a carrier ring support surface encircling the central surface region; and a carrier ring disposed on the carrier ring support surface. The carrier ring comprises an annular disk body comprising an annular wafer support region, an annular peripheral region, and an annular transition region between the annular wafer support region and the annular peripheral region. The annular peripheral region comprises a top carrier ring surface. The annular wafer support region has a lower carrier ring surface that is in physical contact with a wafer during processing. The annular transition region comprises a curved slope between the top carrier ring surface and the lower carrier ring surface.
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公开(公告)号：US20210376125A1
公开(公告)日：2021-12-02
申请号：US16914503
申请日：2020-06-29
发明人： Shih-Hsien Huang , Sheng-Hsu Liu , Wen Yi Tan
摘要： A method for fabricating semiconductor device includes the steps of first forming a gate structure on a substrate, forming a spacer adjacent to the gate structure, forming a recess adjacent to the spacer, trimming part of the spacer, and then forming an epitaxial layer in the recess. Preferably, the semiconductor device includes a first protrusion adjacent to one side of the epitaxial layer and a second protrusion adjacent to another side of the epitaxial layer, the first protrusion includes a V-shape under the spacer and an angle included by the V-shape is greater than 30 degrees and less than 90 degrees.
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公开(公告)号：US20210279315A1
公开(公告)日：2021-09-09
申请号：US16842750
申请日：2020-04-07
发明人： CHAO WU , Chung-Li Chien , Cheng-Tar Lu , Zi Xin Chen , Sheng Kai Wang , WEN YI TAN
摘要： The invention provides a safety system for a cleanroom, which comprises a cleanroom garment provided with a plurality of RFID (radio frequency identification) tags, a face recognition device arranged at an entrance of the cleanroom, and a first RFID reader arranged beside at least one machine in the cleanroom, wherein the first RFID reader is used for identifying the RFID tags on the cleanroom garment, and a KVM network power interrupter connected to a display screen of the machine.
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公开(公告)号：US20210257249A1
公开(公告)日：2021-08-19
申请号：US16820730
申请日：2020-03-17
发明人： Long Wang , Zijun Sun , Chin-Chun Huang , Hailong Gu , Penghui Lu , WEN YI TAN
IPC分类号： H01L21/762 , H01L21/768
摘要： A method of fabricating a semiconductor device, including a high-voltage device region and a low-voltage device region, includes the steps of: providing a substrate, wherein a bottom mask layer and a top mask layer are sequentially disposed thereon; forming a doped region in the substrate based on a first layout pattern; patterning the substrate based on a second layout pattern to form at least two trenches in the substrate respectively in the high-voltage device region and the low-voltage device region; and patterning the top mask layer in the high-voltage device region based on a third layout pattern to form a patterned top mask layer and expose the bottom mask layer from the patterned top mask layer, wherein the third layout pattern is generated by comparing the first layout pattern and the second layout pattern and executing a Boolean operation.
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公开(公告)号：US20210242312A1
公开(公告)日：2021-08-05
申请号：US16831817
申请日：2020-03-27
发明人： Sheng-Hsu Liu , Shih-Hsien Huang , WEN YI TAN
IPC分类号： H01L29/10 , H01L29/161 , H01L29/66 , H01L21/762
摘要： A semiconductor transistor is formed on a substrate of a first conductivity type. The substrate has a main surface. An ion well of the second conductivity type is disposed in the substrate. A source region and a drain region spaced apart from the source region are disposed within the ion well. The source region and the drain region have the first conductivity type. An epitaxial channel layer of the first conductivity type is grown from the main surface of the substrate and is disposed between the source region and the drain region. A gate is disposed on the epitaxial channel layer. A gate dielectric layer is disposed between gate and the epitaxial channel layer.
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公开(公告)号：US10954602B1
公开(公告)日：2021-03-23
申请号：US16683225
申请日：2019-11-13
发明人： Shouguo Zhang , Jinggang Li , Yongbo Xu , Xijun Guo , Pao-Chung Lee
摘要： A method of electro-chemical plating is disclosed. The catholyte is delivered to the cathode chamber. The catholyte is controlled at a first temperature before flowing into the cathode chamber. The anolyte is provided at room temperature. The temperature of the anolyte is lowered from the room temperature to a second temperature before delivering into the anode chamber. The second temperature is equal to or lower than the first temperature. The plating surface of the substrate is immersed in the electrolyte. The substrate is biased to a direct current (DC) voltage. The biased substrate attracts ions of the metal in the electrolyte toward the plating surface so as to electroplating the metal onto the substrate.
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