公开(公告)号：US08373228B2

公开(公告)日：2013-02-12

申请号：US12687607

申请日：2010-01-14

Applicant: Bin Yang ,  Rohit Pal ,  Michael Hargrove

Inventor： Bin Yang ,  Rohit Pal ,  Michael Hargrove

IPC: H01L27/12

CPC classification number: H01L21/84 ,  H01L21/845 ,  H01L23/485 ,  H01L27/12 ,  H01L27/1211

Abstract: A method of fabricating a semiconductor device with back side conductive plugs is provided here. The method begins by forming a gate structure overlying a semiconductor-on-insulator (SOI) substrate. The SOI substrate has a support layer, an insulating layer overlying the support layer, an active semiconductor region overlying the insulating layer, and an isolation region outboard of the active semiconductor region. A first section of the gate structure is formed overlying the isolation region and a second section of the gate structure is formed overlying the active semiconductor region. The method continues by forming source/drain regions in the active semiconductor region, and thereafter removing the support layer from the SOI substrate. Next, the method forms conductive plugs for the gate structure and the source/drain regions, where each of the conductive plugs passes through the insulating layer.

Abstract translation: 此处提供制造具有背面导电插头的半导体器件的方法。 该方法通过形成覆盖绝缘体上半导体（SOI）衬底的栅极结构开始。 SOI衬底具有支撑层，覆盖在支撑层上的绝缘层，覆盖绝缘层的有源半导体区域和有源半导体区域外侧的隔离区域。 栅极结构的第一部分形成在隔离区域的上方，栅极结构的第二部分形成在有源半导体区域的上方。 该方法通过在有源半导体区域中形成源极/漏极区域继续，然后从SOI衬底去除支撑层。 接下来，该方法形成用于栅极结构和源极/漏极区域的导电插塞，其中每个导电插塞穿过绝缘层。

公开(公告)号：US08363278B2

公开(公告)日：2013-01-29

申请号：US11918077

申请日：2006-03-31

Applicant: Zhihong Liu ,  Feng Chen ,  Bin Yang

Inventor： Zhihong Liu ,  Feng Chen ,  Bin Yang

IPC: G06K15/00 ,  G06K9/00 ,  G03G13/04

CPC classification number: H04N1/4052

Abstract: The present invention relates to a method and apparatus capable of generating frequency-modulation halftone dots in high speed and belongs to the field of the digital image halftone. In the prior art, read-write operation is usually carried out many times in error rows during processing each pixel so that halftone dots are generated in low speed. In the method according to the present invention, the error generated by the current pixel is buffered in a register file and the final accumulated error values are written in the error rows only after all of the relative pixels are processed. Thus, read-write operation is carried out only once in the error rows for processing each pixel. The present invention also provides an apparatus to implement the method. The apparatus comprises an error row memory, an error buffer register file, a gray generation circuit, a threshold comparison circuit, an error generation circuit, an error buffer register file control circuit, and an error row control circuit. The method and apparatus according to the present invention decrease the steps in operation and improve the speed for generating the frequency-modulation halftone dots.

Abstract translation: 本发明涉及能够高速产生调频半色调点的属于数字图像半色调的领域的方法和装置。 在现有技术中，在处理每个像素期间，读写操作通常在错误行中进行多次，使得半色调点以低速生成。 在根据本发明的方法中，由当前像素产生的误差被缓存在寄存器文件中，并且只有在处理了所有相对像素之后才将最终的累积误差值写入误差行。 因此，在用于处理每个像素的错误行中仅执行一次读写操作。 本发明还提供了一种实现该方法的装置。 该装置包括错误行存储器，错误缓冲寄存器文件，灰色生成电路，阈值比较电路，错误产生电路，错误缓冲寄存器文件控制电路和错误行控制电路。 根据本发明的方法和装置降低了操作步骤，提高了生成调频半色调点的速度。

公开(公告)号：US20130020705A1

公开(公告)日：2013-01-24

申请号：US13186519

申请日：2011-07-20

Applicant: Emre Alptekin ,  Viraj Y. Sardesai ,  Cung D. Tran ,  Bin Yang

Inventor： Emre Alptekin ,  Viraj Y. Sardesai ,  Cung D. Tran ,  Bin Yang

IPC: H01L21/28 ,  H01L23/50

CPC classification number: H01L23/485 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/26566 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/28518 ,  H01L21/76814 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Methods form an integrated circuit structure by forming at least a portion of a plurality of devices within and/or on a substrate and patterning trenches in an inter-layer dielectric layer on the substrate adjacent the devices. The patterning forms relatively narrow trenches and relatively wide trenches. The methods then perform an angled implant of a compensating material into the trenches. The angle of the angled implant implants a greater concentration of the compensating material in the regions of the substrate at the bottom of the wider trenches relative to an amount of compensating material implanted in the regions of the substrate at the bottom of the narrower trenches. The methods then deposit a metallic material within the trenches and heat the metallic material to form silicide from the metallic material.

Abstract translation: 方法通过在衬底内和/或衬底上形成多个器件的至少一部分形成集成电路结构，并且在邻近器件的衬底上的层间电介质层中图案化沟槽。 图案形成相对较窄的沟槽和较宽的沟槽。 然后，所述方法对沟槽进行补偿材料的成角度注入。 成角度的植入物的角度相对于在较窄沟槽的底部注入衬底的区域中的补偿材料的量，在较宽沟槽底部的衬底区域中植入更大浓度的补偿材料。 然后，该方法将金属材料沉积在沟槽内，并加热金属材料以从金属材料形成硅化物。

公开(公告)号：US20120329707A1

公开(公告)日：2012-12-27

申请号：US13494480

申请日：2012-06-12

Applicant: Richard D. DiMARCHI ,  David L. SMILEY ,  Bin YANG

Inventor： Richard D. DiMARCHI ,  David L. SMILEY ,  Bin YANG

IPC: A61K38/26 ,  A61P3/10 ,  A61P3/04 ,  A61P3/00 ,  A61P25/28 ,  C07K19/00 ,  C07K17/10 ,  C07K17/08 ,  C07K14/605 ,  A61P1/16 ,  B82Y5/00

CPC classification number: C07K14/605 ,  A61K38/00 ,  A61K47/60 ,  C07K2319/00 ,  G01N33/74 ,  G01N2333/605 ,  G01N2800/042 ,  G01N2800/085 ,  G01N2800/2821 ,  G01N2800/2835

Abstract: Provided herein are peptides and variant peptides that exhibit enhanced activity at the GLP-1 receptor, as compared to native glucagon.

公开(公告)号：US08274498B2

公开(公告)日：2012-09-25

申请号：US11982870

申请日：2007-11-05

Applicant: Gang-Qiang Zheng ,  Bin Yang

Inventor： Gang-Qiang Zheng ,  Bin Yang

IPC: G09G5/00

CPC classification number: H04N5/2628 ,  H04N2101/00

Abstract: An exemplary display system (2) includes a display device (23), an image sensor (20), and a microprocessor unit (21). The image sensor includes an image sensor unit (24) and a digital signal processor unit (22) integrated therein. The image sensor unit is configured for generating a current. The digital signal processor includes a size regulator (221) configured for receiving the current, generating an analog image signal according to the current, and providing the analog image signal to the display device. The microprocessor unit is configured for initializing the image sensor unit.

Abstract translation: 示例性显示系统（2）包括显示设备（23），图像传感器（20）和微处理器单元（21）。 图像传感器包括集成在其中的图像传感器单元（24）和数字信号处理器单元（22）。 图像传感器单元被配置为产生电流。 数字信号处理器包括：尺寸调节器（221），被配置为接收电流，根据电流产生模拟图像信号，并将模拟图像信号提供给显示装置。 微处理器单元被配置为初始化图像传感器单元。

公开(公告)号：US20120220095A1

公开(公告)日：2012-08-30

申请号：US13467730

申请日：2012-05-09

Applicant: Man Fai NG ,  Bin YANG

Inventor： Man Fai NG ,  Bin YANG

IPC: H01L21/336

CPC classification number: H01L21/76224 ,  H01L21/76283 ,  H01L21/823807 ,  H01L21/823878 ,  H01L21/84

Abstract: A fabrication method for a semiconductor device structure is provided. The device structure has a layer of silicon and a layer of silicon dioxide overlying the layer of silicon, and the method begins by forming an isolation recess by removing a portion of the silicon dioxide and a portion of the silicon. The isolation recess is filled with stress-inducing silicon nitride and, thereafter, the silicon dioxide is removed such that the stress-inducing silicon nitride protrudes above the silicon. Next, the exposed silicon is thermally oxidized to form silicon dioxide hardmask material overlying the silicon. Thereafter, a first portion of the silicon dioxide hardmask material is removed to reveal an accessible surface of the silicon, while leaving a second portion of the silicon dioxide hardmask material intact. Next, silicon germanium is epitaxially grown from the accessible surface of the silicon.

公开(公告)号：US20120190192A1

公开(公告)日：2012-07-26

申请号：US13012043

申请日：2011-01-24

Applicant: Christian Lavoie ,  Tak H. Ning ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

Inventor： Christian Lavoie ,  Tak H. Ning ,  Ahmet S. Ozcan ,  Bin Yang ,  Zhen Zhang

IPC: H01L21/44

CPC classification number: H01L21/28518

Abstract: In one exemplary embodiment, a program storage device readable by a machine, tangibly embodying a program of instructions executable by the machine for performing operations, said operations including: depositing a first layer having a first metal on a surface of a semiconductor structure, where depositing the first layer creates a first intermix region at an interface of the first layer and the semiconductor structure; removing a portion of the deposited first layer to expose the first intermix region; depositing a second layer having a second metal on the first intermix region, where depositing the second layer creates a second intermix region at an interface of the second layer and the first intermix region; removing a portion of the deposited second layer to expose the second intermix region; and performing at least one anneal on the semiconductor structure.

公开(公告)号：US20120181697A1

公开(公告)日：2012-07-19

申请号：US13006664

申请日：2011-01-14

Applicant: Christian Lavoie ,  Ahmet S. Ozcan ,  Zhen Zhang ,  Bin Yang

Inventor： Christian Lavoie ,  Ahmet S. Ozcan ,  Zhen Zhang ,  Bin Yang

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L21/768 ,  H01L21/28518 ,  H01L23/485 ,  H01L29/456 ,  H01L29/66545 ,  H01L29/66575 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a metal semiconductor alloy that includes forming an intermixed metal semiconductor region to a first depth of a semiconductor substrate without thermal diffusion. The intermixed metal semiconductor region is annealed to form a textured metal semiconductor alloy. A second metal layer is formed on the textured metal semiconductor alloy. The second metal layer on the textured metal semiconductor alloy is then annealed to form a metal semiconductor alloy contact, in which metal elements from the second metal layer are diffused through the textured metal semiconductor alloy to provide a templated metal semiconductor alloy. The templated metal semiconductor alloy includes a grain size that is greater than 2× for the metal semiconductor alloy, which has a thickness ranging from 15 nm to 50 nm.

Abstract translation: 一种形成金属半导体合金的方法，其包括在半导体衬底的第一深度上形成混合金属半导体区域而没有热扩散。 将混合后的金属半导体区域退火以形成织构化的金属半导体合金。 在纹理金属半导体合金上形成第二金属层。 纹理金属半导体合金上的第二金属层然后退火以形成金属半导体合金接触，其中来自第二金属层的金属元素通过织构化金属半导体合金扩散以提供模板化的金属半导体合金。 模板化金属半导体合金的厚度范围为15nm〜50nm的金属半导体合金的晶粒尺寸大于2×。

公开(公告)号：US08217463B2

公开(公告)日：2012-07-10

申请号：US13021403

申请日：2011-02-04

Applicant: Rohit Pal ,  Michael Hargrove ,  Frank Bin Yang

Inventor： Rohit Pal ,  Michael Hargrove ,  Frank Bin Yang

IPC: H01L29/66

CPC classification number: H01L29/66651 ,  H01L21/28123 ,  H01L21/28194 ,  H01L21/28247 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/517

Abstract: Methods for protecting gate stacks during fabrication of semiconductor devices and semiconductor devices fabricated from such methods are provided. Methods for fabricating a semiconductor device include providing a semiconductor substrate having an active region and a shallow trench isolation (STI) region. Epitaxial layer is formed on the active region to define a lateral overhang portion in a divot at the active region/STI region interface. A gate stack is formed having a first gate stack-forming layer overlying the semiconductor substrate. First gate stack-forming layer includes a non-conformal layer of metal gate-forming material which is directionally deposited to form a thinned break portion just below the lateral overhang portion. After the step of forming the gate stack, a first portion of the non-conformal layer is in the gate stack and a second portion is exposed. The thinned break portion at least partially isolates the first and second portions during subsequent etch chemistries.

Abstract translation: 提供了在由这些方法制造的半导体器件和半导体器件的制造期间保护栅极堆叠的方法。 制造半导体器件的方法包括提供具有有源区和浅沟槽隔离（STI）区的半导体衬底。 在有源区上形成外延层，以在有源区/ STI区界面上的边界中限定一个横向伸出部分。 形成具有覆盖在半导体衬底上的第一栅叠层形成层的栅叠层。 第一栅极堆叠形成层包括定向沉积以形成刚好在横向突出部分下方的变薄的断裂部分的非保形层的金属栅极形成材料。 在形成栅极堆叠的步骤之后，非共形层的第一部分在栅极堆叠中并且第二部分被暴露。 减薄断裂部分在随后的蚀刻化学过程中至少部分地隔离第一和第二部分。

公开(公告)号：USD662956S1

公开(公告)日：2012-07-03

申请号：US29363307

申请日：2010-06-08

Applicant: Chih-Ming Lai ,  Hong-Bin Yang

Designer： Chih-Ming Lai ,  Hong-Bin Yang