公开(公告)号：US20100054037A1

公开(公告)日：2010-03-04

申请号：US12615374

申请日：2009-11-10

Applicant: JUNG-WOO LEE ,  JAE-YONG JEONG

Inventor： JUNG-WOO LEE ,  JAE-YONG JEONG

IPC: G11C16/04

CPC classification number: G11C11/5642 ,  G11C11/5628 ,  G11C2211/5633

Abstract: A flash memory device including memory cells, each memory cell configured to store bits, a sensing circuit configured to sequentially sense, for each memory cell, sets of the bits of the memory cell, a data rearrangement unit configured to receive words of data and to rearrange bits of the words to be stored in the memory cells, and an output circuit configured to output a group of the words using the sets of bits from one sensing, at least as early as during a subsequent sensing of sets of bits.

Abstract translation: 一种闪速存储器件，包括存储器单元，每个存储器单元被配置为存储位;感测电路，被配置为对每个存储器单元依次感测存储器单元的位组;数据重排单元，被配置为接收数据字， 重新排列要存储在存储单元中的字的比特，以及输出电路，其被配置为至少在随后感测位组期间早期使用来自一次感测的比特集来输出一组单词。

公开(公告)号：US07668015B2

公开(公告)日：2010-02-23

申请号：US12005366

申请日：2007-12-27

Applicant: Jae-phil Kong ,  Heung-soo Lim ,  Jae-yong Jeong ,  Chi-weon Yoon

Inventor： Jae-phil Kong ,  Heung-soo Lim ,  Jae-yong Jeong ,  Chi-weon Yoon

IPC: G11C16/04

CPC classification number: G11C11/5628

Abstract: In a method of driving a nonvolatile memory device a first data state is determined from among the plurality of data states. The number of simultaneously programmed bits is set according to the determined first data state and a scanning operation is performed on data input from an external device to search data bits to be programmed. The searched data bits are programmed in response to the number of simultaneously programmed bits. The number of simultaneously programmed bits corresponding to the first data state is different from a number of simultaneously programmed bits corresponding to at least a second of the plurality of data states.

Abstract translation: 在驱动非易失性存储器件的方法中，从多个数据状态中确定第一数据状态。 根据确定的第一数据状态来设置同时编程的位的数量，并且对从外部设备输入的数据执行扫描操作以搜索要编程的数据位。 搜索到的数据位被编程为响应于同时编程的位的数量。 对应于第一数据状态的同时被编程的位的数量与对应于多个数据状态中的至少一个数据状态的同时被编程的位的数量不同。

公开(公告)号：US07643340B2

公开(公告)日：2010-01-05

申请号：US11946228

申请日：2007-11-28

Applicant: Jae-Phil Kong ,  Jae-Yong Jeong

Inventor： Jae-Phil Kong ,  Jae-Yong Jeong

IPC: G11C16/04

CPC classification number: G11C11/5628

Abstract: A method of programming a selected cell in a multi-level flash memory device comprises determining whether to program an upper bit or a lower bit of a selected memory cell, detecting a current logic state of two bits of data stored in the selected memory cell, determining a target logic state for the upper or lower bit, generating a program voltage and a verify voltage for programming the upper or lower bit to the target logic state, and applying the program voltage and the verify voltage to a word line connected to the selected memory cell.

Abstract translation: 一种在多级闪速存储器件中对所选单元进行编程的方法包括：确定是否编程所选存储单元的高位或低位，检测存储在所选存储单元中的两位数据的当前逻辑状态， 确定上位或下位的目标逻辑状态，产生用于将上位或下位编程为目标逻辑状态的编程电压和验证电压，以及将编程电压和验证电压施加到连接到所选择的字线的字线 记忆单元

公开(公告)号：US07602650B2

公开(公告)日：2009-10-13

申请号：US11847388

申请日：2007-08-30

Applicant: Kee-Ho Jung ,  Jae-Yong Jeong ,  Chi-Weon Yoon

Inventor： Kee-Ho Jung ,  Jae-Yong Jeong ,  Chi-Weon Yoon

IPC: G11C11/34

CPC classification number: G11C8/10 ,  G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

Abstract: In one aspect, a program method is provided for a flash memory device including a plurality of memory cells each being programmed in one of a plurality of data states. The program method of this aspect includes programming selected memory cells in a first data state, verifying a result of the programming, successively programming selected memory cells in at least two or more data states corresponding to threshold voltages which are lower than a threshold voltage corresponding to the first data state, and verifying results of the successive programming.

Abstract translation: 在一个方面，提供了一种用于闪存器件的程序方法，其包括多个存储器单元，每个存储器单元以多个数据状态中的一个被编程。 该方面的程序方法包括以第一数据状态编程所选择的存储单元，验证编程结果，以对应于低于对应于阈值电压的阈值电压的阈值电压的至少两个或多个数据状态连续地编程所选存储单元 第一数据状态，以及验证连续编程的结果。

公开(公告)号：US20090225603A1

公开(公告)日：2009-09-10

申请号：US12466679

申请日：2009-05-15

Applicant: JIN-YOUNG CHUN ,  JAE-YONG JEONG

Inventor： JIN-YOUNG CHUN ,  JAE-YONG JEONG

IPC: G11C16/04 ,  G11C7/00 ,  G11C8/10

CPC classification number: G11C16/12 ,  G11C16/26 ,  G11C16/3459

Abstract: A nonvolatile memory device includes a command decoder configured to generate a read/write flag signal in response to a read/write command and to generate a reprogram flag signal in response to a reprogram command, and a read/write circuit configured to control reading and writing operations in a memory cell array. The device further includes a read/write controller configured to cause the read/write circuit to perform a reading/writing operation in response to the read/write flag signal provided from the command decoder, and a reprogram controller configured to cause the read/write controller to perform a reprogramming operation in response to the reprogram flag signal. Methods of reprogramming a memory device include determining whether the memory device is in a busy state, delaying a reprogramming operation if the memory device is in a busy state, and executing the reprogramming operation when the memory device has turned to a standby state from the busy state.

Abstract translation: 非易失性存储器件包括：命令解码器，被配置为响应于读/写命令产生读/写标志信号，并且响应于重编程命令产生再编程标志信号;以及读/写电路，被配置为控制读/ 在存储单元阵列中进行写操作。 该装置还包括读/写控制器，其被配置为使得读/写电路响应于从命令解码器提供的读/写标志信号执行读/写操作;以及重新编程控制器，其被配置为使读/ 控制器响应于重新编程标志信号执行重新编程操作。 重新编程存储器件的方法包括：确定存储器件是否处于忙状态，如果存储器件处于忙状态，则延迟重新编程操作，并且当存储器件已经从忙时转为待机状态时执行重新编程操作 州。

公开(公告)号：US20090003056A1

公开(公告)日：2009-01-01

申请号：US12129820

申请日：2008-05-30

Applicant: Jin-Young CHUN ,  Jae-Yong JEONG ,  Chi-Weon YOON

Inventor： Jin-Young CHUN ,  Jae-Yong JEONG ,  Chi-Weon YOON

IPC: G11C16/06 ,  G11C16/00

CPC classification number: G11C11/5628 ,  G11C16/3454 ,  G11C2211/5621

Abstract: Disclosed is a nonvolatile memory device and programming method of a nonvolatile memory device. The programming method of the nonvolatile memory device includes conducting a first programming operation for a memory cell, retrieving original data from the memory cell after the first programming operation, and conducting a second programming operation with reference to the original data and a second verifying voltage higher than a first verifying voltage of the first programming operation.

Abstract translation: 公开了一种非易失性存储器件的非易失性存储器件和编程方法。 非易失性存储器件的编程方法包括对存储器单元执行第一编程操作，在第一编程操作之后从存储单元检索原始数据，并参考原始数据和第二验证电压进行第二编程操作 比第一编程操作的第一验证电压。

公开(公告)号：US07457168B2

公开(公告)日：2008-11-25

申请号：US11871297

申请日：2007-10-12

Applicant: Jae-Yong Jeong ,  Young-Ho Lim

Inventor： Jae-Yong Jeong ,  Young-Ho Lim

IPC: G11C11/34 ,  G11C16/04 ,  G11C8/00

CPC classification number: G11C16/3409 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/344 ,  G11C16/3445

Abstract: Disclosed is a non-volatile memory device and a method of erasing the non-volatile memory device. An erase voltage is simultaneously applied to a plurality of sectors contained in the non-volatile memory device. Then, erase validation is sequentially performed for each of the plurality sectors and results of the erase validation are stored in a plurality of pass information registers. According to the results stored in the pass information registers, sectors which were not successfully erased are simultaneously re-erased and then sequentially re-validated until no such “failed sectors” remain in the non-volatile memory device. Upon eliminating the “failed sectors” from the non-volatile memory device, a post-program operation is sequentially performed on each of the plurality of sectors.

Abstract translation: 公开了一种非易失性存储器件和擦除非易失性存储器件的方法。 同时将擦除电压施加到包含在非易失性存储器件中的多个扇区。 然后，针对多个扇区中的每一个依次执行擦除验证，并将擦除确认的结果存储在多个通过信息寄存器中。 根据存储在通过信息寄存器中的结果，同时重新擦除未成功擦除的扇区，然后顺序重新验证，直到在非易失性存储器件中不存在这样的“故障扇区”为止。 在从非易失性存储器件消除“故障扇区”时，对多个扇区中的每一个依次执行后编程操作。

公开(公告)号：US07379372B2

公开(公告)日：2008-05-27

申请号：US11181163

申请日：2005-07-13

Applicant: Jae-Yong Jeong

Inventor： Jae-Yong Jeong

IPC: G11C5/14

CPC classification number: G11C16/10 ,  G11C16/32

Abstract: An accelerated bit scanning nonvolatile memory device and method. A nonvolatile memory device including a memory cell array including a plurality of memory cells, each memory cell corresponding to program data, a data scanning unit to detect the program data having a first value, and a programming unit to program the memory cells corresponding to the detected portions of the program data responsive to the scanning.

Abstract translation: 一种加速位扫描非易失存储器件及方法。 一种包括存储单元阵列的非易失性存储器件，包括多个存储器单元，与程序数据相对应的每个存储单元，用于检测具有第一值的程序数据的数据扫描单元，以及编程单元， 检测到响应于扫描的节目数据的部分。

公开(公告)号：US07372733B2

公开(公告)日：2008-05-13

申请号：US11598788

申请日：2006-11-14

Applicant: Jong In Choi ,  Jae Yong Jeong

Inventor： Jong In Choi ,  Jae Yong Jeong

IPC: G11C16/04

CPC classification number: G11C16/16 ,  G11C16/04 ,  G11C16/344 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

Abstract: A non-volatile semiconductor memory device comprises a plurality of memory sectors arranged in different memory banks having different bulk regions. The memory cells can be erased using a first mode erase operation, which determines different erase pass voltages for the respective memory sectors by successively increasing a bank voltage applied to each sector until the number of failed cells in each sector falls below a first failed cell threshold value, and a second mode erase operation, which applies the different erase pass voltages to the respective memory sectors for successively increasing periods of time until the number of failed cells in each sector falls below a second failed cell threshold value.

Abstract translation: 非易失性半导体存储器件包括布置在具有不同体积区域的不同存储体中的多个存储器扇区。 可以使用第一模式擦除操作来擦除存储器单元，该第一模式擦除操作通过连续增加施加到每个扇区的存储体电压来确定各个存储器扇区的不同擦除通过电压，直到每个扇区中的故障单元的数量低于第一故障单元阈值 值和第二模式擦除操作，其将不同的擦除遍电压施加到各个存储器扇区，用于连续增加的时间段，直到每个扇区中的故障小区的数量低于第二故障小区阈值。

公开(公告)号：US07359240B2

公开(公告)日：2008-04-15

申请号：US11322983

申请日：2005-12-29

Applicant: Jung-Woo Lee ,  Jae-Yong Jeong

Inventor： Jung-Woo Lee ,  Jae-Yong Jeong

IPC: G11C11/34

CPC classification number: G11C11/5642 ,  G11C11/5628 ,  G11C2211/5633

Abstract: A flash memory device including memory cells, each memory cell configured to store bits, a sensing circuit configured to sequentially sense, for each memory cell, sets of the bits of the memory cell, a data rearrangement unit configured to receive words of data and to rearrange bits of the words to be stored in the memory cells, and an output circuit configured to output a group of the words using the sets of bits from one sensing, at least as early as during a subsequent sensing of sets of bits.

Abstract translation: 一种闪速存储器件，包括存储器单元，每个存储器单元被配置为存储位;感测电路，被配置为对每个存储器单元依次感测存储器单元的位组;数据重排单元，被配置为接收数据字， 重新排列要存储在存储单元中的字的比特，以及输出电路，其被配置为至少在随后感测位组期间早期使用来自一次感测的比特集来输出一组单词。