公开(公告)号：US06937606B2

公开(公告)日：2005-08-30

申请号：US09839010

申请日：2001-04-20

Applicant: Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

Inventor： Claude Basso ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Fabrice Jean Verplanken

IPC: H04L12/56 ,  H04L29/06

CPC classification number: H04L69/16 ,  H04L29/06 ,  H04L49/90 ,  H04L49/9094 ,  H04L69/161 ,  H04L69/166 ,  H04L69/22

Abstract: Data structures, a method, and an associated transmission system for IP fragmentation and IP reassembly on network processors in order to minimize memory allocation requirements. Frame data for IP fragmentation or reassembly on a network processor is read into buffers to which are associated various control structures. The control structures permit IP fragmentation or reassembly to be accomplished without creating multiple copies of the frame or fragments.

Abstract translation: 数据结构，方法和相关的传输系统，用于网络处理器上的IP分段和IP重组，以最大限度地减少内存分配要求。 在网络处理器上进行IP分片或重组的帧数据被读入到与各种控制结构相关联的缓冲器中。 控制结构允许在不产生帧或片段的多个副本的情况下实现IP分片或重组。

公开(公告)号：US06862292B1

公开(公告)日：2005-03-01

申请号：US09548910

申请日：2000-04-13

Applicant: Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

Inventor： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

IPC: H04L12/56 ,  H04Q11/04 ,  H04L12/28

CPC classification number: H04Q11/0478 ,  H04L47/2425 ,  H04L47/50 ,  H04L47/52 ,  H04L47/627 ,  H04L2012/5636 ,  H04L2012/5649 ,  H04L2012/5651 ,  H04L2012/5679 ,  H04L2012/5681

Abstract: A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. The priorities in the preferred embodiment include a low latency service, a minimum bandwidth, a weighted fair queueing and a system for preventing a user from continuing to exceed his service levels over an extended period. The present invention includes a plurality of calendars with different service rates to allow a user to select the service rate which he desires. If a customer has chosen a high bandwidth for service, the customer will be included in a calendar which is serviced more often than if the customer has chosen a lower bandwidth.

Abstract translation: 一种将信息单元从网络处理器移动到数据传输网络的系统和方法，其以容纳几个不同级别的服务的优先顺序排列。 本发明包括一种方法和系统，用于根据存储的与信息单元的各种源相关联的优先级来调度来自网络处理单元的处理的信息单元（或帧）的出口。 优选实施例中的优先级包括低延迟服务，最小带宽，加权公平排队以及用于在较长时间内防止用户继续超过其服务水平的系统。 本发明包括具有不同服务速率的多个日历，以允许用户选择他所期望的服务速率。 如果客户选择了高带宽的服务，客户将被包含在比客户选择较低带宽的情况下更频繁地服务的日历。

公开(公告)号：US06795870B1

公开(公告)日：2004-09-21

申请号：US09548907

申请日：2000-04-13

Applicant: Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

Inventor： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

IPC: G06F300

CPC classification number: H04L47/568 ,  H04L47/50

Abstract: A system and method uses grouped calendars, flow queues, pointers and stored rules to process information packets so that different flow control characteristics associated with the information units are maintained.

Abstract translation: 系统和方法使用分组的日历，流队列，指针和存储的规则来处理信息分组，从而保持与信息单元相关联的不同流控制特性。

公开(公告)号：US06532185B2

公开(公告)日：2003-03-11

申请号：US09792605

申请日：2001-02-23

Applicant: Jean Louis Calvignac ,  Peter Irma August Barri ,  Ivan Oscar Clemminck ,  Kent Harold Haselhorst ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Bart Joseph Gerard Pauwels ,  Fabrice Jean Verplanken ,  Miroslav Vrana

Inventor： Jean Louis Calvignac ,  Peter Irma August Barri ,  Ivan Oscar Clemminck ,  Kent Harold Haselhorst ,  Marco C. Heddes ,  Joseph Franklin Logan ,  Bart Joseph Gerard Pauwels ,  Fabrice Jean Verplanken ,  Miroslav Vrana

IPC: G11C800

CPC classification number: H04L49/901 ,  G06F12/0607 ,  H04L49/90 ,  H04L49/9031

Abstract: Network processors commonly utilize DRAM chips for the storage of data. Each DRAM chip contains multiple banks for quick storage of data and access to that data. Latency in the transfer or the ‘write’ of data into memory can occur because of a phenomenon referred to as memory bank polarization. By a procedure called quadword rotation, this latency effect is effectively eliminated. Data frames received by the network processor are transferred to a receive queue (FIFO). The frames are divided into segments that are written into the memory of the DRAM in accordance with a formula that rotates the distribution of each segment into the memory banks of the DRAM.

公开(公告)号：US07984038B2

公开(公告)日：2011-07-19

申请号：US12103140

申请日：2008-04-15

Applicant: Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Antonios Maragkos ,  Piyush Chunilal Patel ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

Inventor： Brian Mitchell Bass ,  Jean Louis Calvignac ,  Marco C. Heddes ,  Antonios Maragkos ,  Piyush Chunilal Patel ,  Michael Steven Siegel ,  Fabrice Jean Verplanken

IPC: G06F17/30

CPC classification number: G06F17/30985 ,  H04L45/7457 ,  Y10S707/99931 ,  Y10S707/99933 ,  Y10S707/99936 ,  Y10S707/99942 ,  Y10S707/99943 ,  Y10S707/99945

Abstract: Novel data structures, methods and apparatus for finding the longest prefix match search when searching tables with variable length patterns or prefixes. To find the exact match or the best matching prefix, patterns have to be compared a bit at a time until the exact or first match is found. This requires “n” number of comparisons or memory accesses to identify the closest matching pattern. The trees are built in such a way that the matching result is guaranteed to be a best match, whether it is an exact match or a longest prefix match. Using the trail of all the birds and associated prefix lengths enables determination of the correct prefix result from the trail. By construction, the search tree provides the best matching prefix at or after the first compare during walking of the trail or tree.

Abstract translation: 当搜索具有可变长度模式或前缀的表时，用于查找最长前缀的新型数据结构，方法和装置匹配搜索。 要找到完全匹配或最匹配的前缀，模式必须一次比较一下，直到发现确切或第一个匹配。 这需要“n”个比较或存储器访问来识别最接近的匹配模式。 树的建立方式使得匹配结果保证是最佳匹配，无论是完全匹配还是最长匹配前缀。 使用所有鸟的踪迹和相关的前缀长度可以确定路线中正确的前缀结果。 通过构建，搜索树在步道或树的步行期间在第一次比较之前或之后提供最佳的匹配前缀。

公开(公告)号：US07953951B2

公开(公告)日：2011-05-31

申请号：US12124396

申请日：2008-05-21

Applicant: Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Gordon Taylor Davis ,  Harm Peter Hofstee ,  Fabrice Jean Verplanken ,  Colin Beaton Verrilli

Inventor： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Gordon Taylor Davis ,  Harm Peter Hofstee ,  Fabrice Jean Verplanken ,  Colin Beaton Verrilli

IPC: G06F12/00

CPC classification number: G06F9/3851 ,  G06F9/3802 ,  G06F9/4843

Abstract: Systems and methods for distributing thread instructions in the pipeline of a multi-threading digital processor are disclosed. More particularly, hardware and software are disclosed for successively selecting threads in an ordered sequence for execution in the processor pipeline. If a thread to be selected cannot execute, then a complementary thread is selected for execution.

Abstract translation: 公开了在多线程数字处理器的流水线中分发线程指令的系统和方法。 更具体地，公开了硬件和软件，用于以有序序列连续选择线程以在处理器管线中执行。 如果要选择的线程无法执行，则选择补充线程执行。

公开(公告)号：US07903687B2

公开(公告)日：2011-03-08

申请号：US11096363

申请日：2005-04-01

Applicant: Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Natarajan Vaidhyanathan ,  Fabrice Jean Verplanken ,  Colin Beaton Verrilli

Inventor： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Natarajan Vaidhyanathan ,  Fabrice Jean Verplanken ,  Colin Beaton Verrilli

IPC: H04J3/16 ,  H04J3/22 ,  H04J3/24

CPC classification number: H04L49/901 ,  H04J3/0632 ,  H04L47/50 ,  H04L49/90 ,  H04L49/9031

Abstract: A method for receiving packets in a computer network are disclosed. The method include providing at least one receive port, a buffer, a scheduler, and a wrap port. The buffer has an input coupled with the at least one receive port and an output. The scheduler has a first input coupled to the output of the buffer, a second input coupled to the wrap port, and an output.

Abstract translation: 公开了一种在计算机网络中接收分组的方法。 该方法包括提供至少一个接收端口，缓冲器，调度器和包装端口。 缓冲器具有与至少一个接收端口和输出端耦合的输入。 调度器具有耦合到缓冲器的输出的第一输入，耦合到包装端口的第二输入和输出。

公开(公告)号：US07782888B2

公开(公告)日：2010-08-24

申请号：US11953820

申请日：2007-12-10

Applicant: Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Natarajan Vaidhyanathan ,  Fabrice Jean Verplanken ,  Colin B. Verrilli

Inventor： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Natarajan Vaidhyanathan ,  Fabrice Jean Verplanken ,  Colin B. Verrilli

IPC: H04L12/28

CPC classification number: H04L12/40032 ,  H04L12/413 ,  H04L49/90 ,  H04L69/12 ,  H04L69/16 ,  H04L69/161 ,  H04L69/18 ,  H04L69/323 ,  H04L69/324

Abstract: A system and method in accordance with the present invention allows for an adapter to be utilized in a server environment that can accommodate both a 10 G and a 1 G source utilizing the same pins. This is accomplished through the use of a high speed serializer/deserializer (high speed serdes) which can accommodate both data sources. The high speed serdes allows for the use of a relatively low reference clock speed on the NIC to provide the proper clocking of the data sources and also allows for different modes to be set to accommodate the different data sources. Finally the system allows for the adapter to use the same pins for multiple data sources.

Abstract translation: 根据本发明的系统和方法允许在可以使用相同引脚容纳10G和1G源的服务器环境中使用适配器。 这是通过使用可以容纳两个数据源的高速串行器/解串器（高速serdes）来实现的。 高速serdes允许在NIC上使用相对较低的参考时钟速度来提供数据源的适当时钟，并且还允许设置不同的模式以适应不同的数据源。 最后，该系统允许适配器为多个数据源使用相同的引脚。

公开(公告)号：US07697536B2

公开(公告)日：2010-04-13

申请号：US11097051

申请日：2005-04-01

Applicant: Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Ronald Edward Fuhs ,  Natarajan Vaidhyanathan ,  Fabrice Jean Verplanken ,  Colin Beaton Verrilli ,  Scott Michael Willenborg ,  Kyle A. Lucke ,  Harvey G. Kiel

Inventor： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Philippe Damon ,  Ronald Edward Fuhs ,  Natarajan Vaidhyanathan ,  Fabrice Jean Verplanken ,  Colin Beaton Verrilli ,  Scott Michael Willenborg ,  Kyle A. Lucke ,  Harvey G. Kiel

IPC: H04L12/56

CPC classification number: H04L29/06 ,  H04L49/90 ,  H04L69/32

Abstract: Providing communications between operating system partitions and a computer network. In one aspect, an apparatus for distributing network communications among multiple operating system partitions includes a physical port allowing communications between the network and the computer system, and logical ports associated with the physical port, where each logical port is associated with one of the operating system partitions. Each of the logical ports enables communication between a physical port and the associated operating system partition and allows configurability of network resources of the system. Other aspects include a logical switch for logical and physical ports, and packet queues for each connection and for each logical port.

Abstract translation: 提供操作系统分区与计算机网络之间的通信。 一方面，一种用于在多个操作系统分区之间分配网络通信的装置包括允许网络和计算机系统之间的通信的物理端口以及与物理端口相关联的逻辑端口，其中每个逻辑端口与操作系统之一相关联 分区。 每个逻辑端口实现物理端口与相关联的操作系统分区之间的通信，并允许系统的网络资源的可配置性。 其他方面包括用于逻辑和物理端口的逻辑交换机，以及每个连接和每个逻辑端口的分组队列。

公开(公告)号：US07603539B2

公开(公告)日：2009-10-13

申请号：US12039304

申请日：2008-02-28

Applicant: Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Fabrice Jean Verplanken

Inventor： Claude Basso ,  Jean Louis Calvignac ,  Chih-jen Chang ,  Fabrice Jean Verplanken

IPC: G06F12/00

CPC classification number: H04L49/901 ,  H04L49/252 ,  H04L49/30 ,  H04L49/90 ,  H04L69/12 ,  H04L69/22

Abstract: Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.

Abstract translation: 公开了一种用于在网络处理器中实现多帧控制块的系统和方法。 实施例包括用于减少长时间存储器访问到诸如DRAM之类的便宜的存储器的系统和方法。 随着网络中的网络处理器接收数据包，网络处理器为每个数据包形成帧控制块。 帧控制块包含指向存储分组数据的存储器位置的指针，并且因此与分组相关联。 网络处理器将存储在控制存储器中的表控制块中的多个帧控制块相关联。 每个表控制块包括指向表控制块链中的下一个表控制块的存储器位置的指针。 由于帧控制块在表控制块中被存储和访问，因此可能需要较少频率的存储器访问以跟上分组传输的帧速率。