公开(公告)号：US20080195803A1

公开(公告)日：2008-08-14

申请号：US12029665

申请日：2008-02-12

Applicant: Chan-Ik PARK ,  Jin-Wook LEE ,  Byoung-Kook LEE

Inventor： Chan-Ik PARK ,  Jin-Wook LEE ,  Byoung-Kook LEE

IPC: G06F12/00

CPC classification number: G06F12/0866 ,  G06F12/0246 ,  G06F2212/222 ,  G06F2212/7201 ,  G06F2212/7203

Abstract: A method for reducing a memory map table search time when employing a semiconductor memory device as a temporary memory of large capacity storage device, and a semiconductor memory device therefore, are provided. A MAP RAM is prepared for storing map table data related to the nonvolatile memory area in the volatile memory area. At an initial power-up operation, it is determined whether a logical address is searched for from the map table data while the map table data existing in a map storage area of the nonvolatile memory area is loaded into the MAP RAM. A physical address corresponding to the logical address is provided as an output, when the logical address is searched for. Search time for a memory map table is reduced and read performance in a high speed map information search is increased.

Abstract translation: 提供一种用于在采用半导体存储器件作为大容量存储器件的临时存储器时减少存储器映射表搜索时间的方法，以及半导体存储器件。 准备MAP RAM用于存储与易失性存储器区域中的非易失性存储器区域相关的映射表数据。 在初始加电操作中，确定存在于非易失存储器区域的映射存储区域中的映射表数据是否被加载到MAP RAM中时，从地图表数据中搜索逻辑地址。 当搜索逻辑地址时，提供与逻辑地址对应的物理地址作为输出。 降低了存储器映射表的搜索时间，并且增加了在高速地图信息搜索中的读取性能。

公开(公告)号：US20080191868A1

公开(公告)日：2008-08-14

申请号：US11892474

申请日：2007-08-23

Applicant: Jin Wook Lee ,  Su-Myeon Kim ,  Sun Shin An ,  Won Keun Kong ,  Hun Lim ,  Kyung Soo Lim ,  Sang Bin Lee

Inventor： Jin Wook Lee ,  Su-Myeon Kim ,  Sun Shin An ,  Won Keun Kong ,  Hun Lim ,  Kyung Soo Lim ,  Sang Bin Lee

IPC: G08B29/00

CPC classification number: H04L12/66

Abstract: A data aggregation method and data aggregation apparatus are provided. More particularly the data aggregation method includes: generating a plurality of data aggregation trees according to connection relationships between clusters that constitute a sensor network using a geographical code (GGC), selecting a single activation zone for each of the clusters which configures each of the plurality of data aggregation trees, selecting a maximum energy tree having a maximum total residual energy from the plurality of data aggregation trees, based on the single activation zone, and generating a tree list including activation zone information which corresponds to the maximum energy tree, and information about the maximum energy tree.

Abstract translation: 提供了一种数据聚合方法和数据聚合装置。 更具体地，数据聚合方法包括：根据构成使用地理码（GGC）的传感器网络的集群之间的连接关系生成多个数据聚合树，为配置每个多个集群的每个集群选择单个激活区域 的数据聚合树，基于单个激活区域选择具有来自多个数据聚合树的最大总剩余能量的最大能量树，并且生成包括对应于最大能量树的激活区域信息的树列表和信息 关于最大能量树。

公开(公告)号：US07372754B2

公开(公告)日：2008-05-13

申请号：US11354917

申请日：2006-02-16

Applicant: Sang-Won Hwang ,  Jin-Wook Lee

Inventor： Sang-Won Hwang ,  Jin-Wook Lee

IPC: G11C7/00

CPC classification number: G11C16/12 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/30 ,  G11C16/32

Abstract: A nonvolatile memory device includes a nonvolatile memory cell array including a plurality of nonvolatile memory cells connected to a plurality of word lines, a word line voltage generator configured to generate first and second sequences of voltage pulses. The device selectively supplies one of the first and second sequences of voltage pulses to a selected one of the word lines to program the nonvolatile memory cells connected to the selected word line. A slope of at least one voltage pulse of the first sequence of voltage pulses is greater than a slope of at least one voltage pulse of the second sequence of voltage pulses. In general, the first sequence is applied to word lines far away from the string select line (SSL), and the second sequence is applied to word lines that are close to the SSL.

Abstract translation: 非易失性存储器件包括非易失性存储单元阵列，包括连接到多个字线的多个非易失性存储器单元，字线电压发生器，被配置为产生第一和第二电压脉冲序列。 该装置选择性地将第一和第二电压脉冲序列中的一个提供给选定的字线之一，以编程连接到所选字线的非易失存储器单元。 电压脉冲的第一序列的至少一个电压脉冲的斜率大于第二电压脉冲序列的至少一个电压脉冲的斜率。 通常，第一个序列应用于远离字符串选择行（SSL）的字线，第二个序列应用于接近SSL的字线。

公开(公告)号：US07369442B2

公开(公告)日：2008-05-06

申请号：US11303557

申请日：2005-12-15

Applicant: Jin-Wook Lee ,  Jin-Yub Lee

Inventor： Jin-Wook Lee ,  Jin-Yub Lee

IPC: G11C11/03

CPC classification number: G11C16/14

Abstract: A method for discharging an erase voltage of a semiconductor memory device and discharge circuit for performing the method, the method including performing a first discharge on a common source line (CSL) of the semiconductor memory device, comparing the detected CSL voltage with a predetermined reference voltage, and performing a second discharge on the CSL when the detected CSL voltage is lower than a predetermined reference voltage.

Abstract translation: 一种用于对用于执行该方法的半导体存储器件和放电电路的擦除电压进行放电的方法，该方法包括在半导体存储器件的公共源极线（CSL）上执行第一次放电，将检测到的CSL电压与预定的参考值进行比较 电压，并且当检测到的CSL电压低于预定参考电压时，在CSL上执行第二放电。

公开(公告)号：US20080100532A1

公开(公告)日：2008-05-01

申请号：US11723286

申请日：2007-03-19

Applicant: Jin Wook Lee ,  Su Myeon Kim ,  Hun Lim ,  Won Keun Kong

Inventor： Jin Wook Lee ,  Su Myeon Kim ,  Hun Lim ,  Won Keun Kong

IPC: G09G5/00

CPC classification number: H04L12/1881 ,  H04L12/1813 ,  H04L12/189

Abstract: A presentation apparatus includes: a communication connection establishing unit establishing a communication connection with a plurality of receiving terminals and a source terminal, the source terminal having a token corresponding to an authority of controlling a presentation; a presentation data relay unit receiving presentation data from the source terminal, broadcasting a presentation image to the plurality of receiving terminals to display the presentation image of the received presentation data on each screen of the plurality of receiving terminals, and broadcasting voice information to the source terminal and the plurality of receiving terminals to output, from each terminal, the voice information being inputted from any one of the source terminal and the plurality of receiving terminals; and a presentation control unit controlling a transmission/reception of the presentation image and the voice information, and controlling a receiving terminal requesting the token to obtain the token.

Abstract translation: 呈现装置包括：通信连接建立单元，建立与多个接收终端和源终端的通信连接，源终端具有对应于控制演示的权限的令牌; 呈现数据中继单元，从源终端接收演示数据，向多个接收终端广播呈现图像，以在多个接收终端的每个屏幕上显示所接收的呈现数据的呈现图像，并向该源广播语音信息 终端和多个接收终端从每个终端输出从源终端和多个接收终端中的任一个输入的语音信息; 以及控制所述呈现图像和所述语音信息的发送/接收的呈现控制单元，以及控制请求所述令牌以获得所述令牌的接收终端。

公开(公告)号：US07351622B2

公开(公告)日：2008-04-01

申请号：US11490613

申请日：2006-07-21

Applicant: Gyoung-Ho Buh ,  Chang-Woo Ryoo ,  Yu-Gyun Shin ,  Tai-Su Park ,  Jin-Wook Lee

Inventor： Gyoung-Ho Buh ,  Chang-Woo Ryoo ,  Yu-Gyun Shin ,  Tai-Su Park ,  Jin-Wook Lee

IPC: H01L21/84 ,  H01L21/8234 ,  H01L21/336 ,  H01L21/00

CPC classification number: H01L29/7851 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/66803

Abstract: A method of forming a semiconductor device includes forming a three-dimensional structure formed of a semiconductor on a semiconductor substrate, and isotropically doping the three-dimensional structure by performing a plasma doping process using a first source gas and a second source gas. The first source gas includes n-type or p-type impurity elements, and the second source gas includes a dilution element regardless of the electrical characteristic of a doped region.

Abstract translation: 形成半导体器件的方法包括在半导体衬底上形成由半导体形成的三维结构，并且通过使用第一源气体和第二源气体进行等离子体掺杂工艺，对三维结构进行各向同性地掺杂。 第一源气体包括n型或p型杂质元素，第二源气体包括稀释元件，而与掺杂区域的电特性无关。

公开(公告)号：US20070091694A1

公开(公告)日：2007-04-26

申请号：US11454481

申请日：2006-06-16

Applicant: Jin-Wook Lee ,  Jin-Yub Lee

Inventor： Jin-Wook Lee ,  Jin-Yub Lee

IPC: G11C5/14

CPC classification number: G11C16/3418 ,  G11C16/26 ,  G11C16/3427

Abstract: A flash memory device includes a memory cell array having a first region and a second region that include memory cells arranged in a plurality of rows and columns; an address storage circuit adapted to store address information for defining the second region; a row decoder circuit adapted to select one of the first and second regions in response to an external address; a voltage generating circuit adapted to generate a read voltage to be provided to a row of the selected region by the row decoder circuit during a read operation; a detecting circuit adapted to detect whether the selected region is included in the second region on the basis of address information and external address information that are stored in the address storage circuit; and a control logic adapted to control the voltage generating circuit in response to an output of the detecting circuit during the read operation. The control logic controls the voltage generating circuit so that a read voltage provided to the row of the second region is lower than a read voltage provided to a row of the first region.

Abstract translation: 闪速存储器件包括具有第一区域和第二区域的存储单元阵列，所述第二区域包括排列成多行和列的存储单元; 地址存储电路，适于存储用于定义第二区域的地址信息; 行解码器电路，其适于响应于外部地址来选择所述第一和第二区域中的一个; 电压发生电路，其适于在读取操作期间由行解码器电路产生要提供给所选区域的行的读取电压; 检测电路，其适于基于存储在所述地址存储电路中的地址信息和外部地址信息来检测所述选择区域是否包括在所述第二区域中; 以及控制逻辑，适于在读取操作期间响应于检测电路的输出来控制电压产生电路。 控制逻辑控制电压产生电路，使得提供给第二区域的行的读取电压低于提供给第一区域的行的读取电压。

公开(公告)号：US20070070127A1

公开(公告)日：2007-03-29

申请号：US11514962

申请日：2006-09-05

Applicant: Jin-wook Lee ,  Sung-joon Park ,  Myong-jong Kwon ,  Yong-shik Park

Inventor： Jin-wook Lee ,  Sung-joon Park ,  Myong-jong Kwon ,  Yong-shik Park

IPC: B41J2/05

CPC classification number: B41J2/1404 ,  B41J2/1603 ,  B41J2/1628 ,  B41J2/1629 ,  B41J2/1631 ,  B41J2/1632 ,  B41J2/1639 ,  B41J2/1645

Abstract: An inkjet printhead and a method of manufacturing the same includes a substrate, an ink chamber to contain ink having a predetermined depth in an upper side of the substrate and an ink feedhole to supply the ink to the ink chamber provided in a lower side of the substrate, a heater formed on the bottom of the ink chamber to heat the ink and to form an ink bubble, and a nozzle layer deposited on the substrate and having a nozzle connected to the ink chamber. The ink chamber is narrower toward the bottom thereof and a sidewall of the ink chamber has a concave round shape.

Abstract translation: 喷墨打印头及其制造方法包括：基板，容纳在基板的上侧具有预定深度的墨水的墨水室;以及用于将油墨供应到设置在基板的下侧的墨水室的墨水供给孔 基板，形成在墨水室的底部以加热墨水并形成墨水泡沫的加热器，以及沉积在基板上并具有连接到墨水腔的喷嘴的喷嘴层。 墨水室朝向其底部较窄，并且墨水室的侧壁具有凹形圆形。

公开(公告)号：US20060284935A1

公开(公告)日：2006-12-21

申请号：US11404803

申请日：2006-04-17

Applicant: Yong-shik Park ,  Myong-jong Kwon ,  Sung-joon Park ,  Jin-wook Lee

Inventor： Yong-shik Park ,  Myong-jong Kwon ,  Sung-joon Park ,  Jin-wook Lee

IPC: B41J2/05

CPC classification number: B41J2/1412 ,  B41J2/14129

Abstract: An inkjet printer head and fabrication method thereof. The inkjet printer head includes a substrate, a thermal layer formed on the substrate to generate thermal energy, a first electrode formed on the thermal layer except at a nozzle forming portion of the thermal layer, and a second electrode extending a predetermined distance to the nozzle forming portion of the thermal layer from a top portion of the first electrode to contact a central portion of the thermal layer. Accordingly, the inkjet printer head has high efficiency and durability.

Abstract translation: 一种喷墨打印机头及其制造方法。 喷墨打印机头包括基板，形成在基板上以产生热能的热层，形成在除了热层的喷嘴形成部分之外的热层上的第一电极以及向喷嘴延伸预定距离的第二电极 从第一电极的顶部形成热层的部分以接触热层的中心部分。 因此，喷墨打印头具有高效率和耐久性。

公开(公告)号：US20060250854A1

公开(公告)日：2006-11-09

申请号：US11303557

申请日：2005-12-15

Applicant: Jin-Wook Lee ,  Jin-Yub Lee

Inventor： Jin-Wook Lee ,  Jin-Yub Lee

IPC: G11C11/34

CPC classification number: G11C16/14

Abstract: Provided is a method for discharging an erase voltage of a semiconductor memory device and discharge circuit for performing the method, the method including performing a first discharge on a common source line (CSL) of the semiconductor memory device, comparing the detected CSL voltage with a predetermined reference voltage, and performing a second discharge on the CSL when the detected CSL voltage is lower than a predetermined reference voltage.

Abstract translation: 提供了一种用于对用于执行该方法的半导体存储器件和放电电路的擦除电压进行放电的方法，该方法包括在半导体存储器件的公共源线（CSL）上执行第一次放电，将检测到的CSL电压与 预定的参考电压，并且当检测到的CSL电压低于预定的参考电压时，在CSL上执行第二次放电。