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    Semiconductor structures including accumulations of silicon boronide and related methods
    1.
    发明申请
    Semiconductor structures including accumulations of silicon boronide and related methods 审中-公开
    半导体结构包括硅化硼的积累和相关方法

    公开(公告)号：US20070215959A1

    公开(公告)日：2007-09-20

    申请号：US11713877

    申请日：2007-03-05

    申请人： Jin-Wook Lee ,  Chang-Woo Ryoo ,  Tai-Su Park ,  U-In Chung ,  Yu-Gyun Shin

    发明人： Jin-Wook Lee ,  Chang-Woo Ryoo ,  Tai-Su Park ,  U-In Chung ,  Yu-Gyun Shin

    IPC分类号： H01L29/94

    CPC分类号： H01L29/4941 ,  H01L21/28061

    摘要： A semiconductor device may include a semiconductor substrate, first and second source/drain regions on a surface of the semiconductor substrate, and a channel region on the surface of the semiconductor substrate with the channel region between the first and second source/drain regions. An insulating layer pattern may be on the channel region, a first conductive layer pattern may be on the insulating layer, and a second conductive layer pattern may be on the first conductive layer pattern. The insulating layer pattern may be between the first conductive layer pattern and the channel region, and the first conductive layer pattern may include boron doped polysilicon with a surface portion having an accumulation of silicon boronide. The first conductive layer pattern may be between the second conductive layer pattern and the insulating layer pattern, and the second conductive layer pattern may include tungsten. Related methods are also discussed.

    摘要翻译： 半导体器件可以包括半导体衬底，半导体衬底的表面上的第一和第二源极/漏极区域以及在第一和第二源极/漏极区域之间具有沟道区域的半导体衬底的表面上的沟道区域。 绝缘层图案可以在沟道区上，第一导电层图案可以在绝缘层上，并且第二导电层图案可以在第一导电层图案上。 绝缘层图案可以在第一导电层图案和沟道区之间，并且第一导电层图案可以包括硼掺杂多晶硅，表面部分具有硅化硼的积累。 第一导电层图案可以在第二导电层图案和绝缘层图案之间，并且第二导电层图案可以包括钨。 还讨论了相关方法。

    Method for forming transistor of semiconductor device
    2.
    发明授权
    Method for forming transistor of semiconductor device 失效
    半导体器件晶体管形成方法

    公开(公告)号：US06667200B2

    公开(公告)日：2003-12-23

    申请号：US10331265

    申请日：2002-12-30

    申请人： Yong Sun Sohn ,  Chang Woo Ryoo ,  Jeong Youb Lee

    发明人： Yong Sun Sohn ,  Chang Woo Ryoo ,  Jeong Youb Lee

    IPC分类号： H01L218238

    CPC分类号： H01L21/28185 ,  H01L21/28202 ,  H01L21/823807 ,  H01L29/105 ,  H01L29/365 ,  H01L29/66651

    摘要： A method for forming a transistor of a semiconductor device, including the step of forming channel layers of a first and a second conductive types, performing high temperature thermal process to form stabilized channel layers and forming an epitaxial channel structure having a super-steep-retrograde &dgr;-doped layer by growing undoped silicon epitaxial layers, treating the entire surface of the resulting structure with hydrogen, forming an epitaxial channel structure by growing undoped silicon epitaxial layers on the stabilized channel layers, forming gate insulating films and gate electrodes on the epitaxial channel structures, re-oxidizing the gate insulating films for repairing damaged portions of the gate insulating films; and forming a source/drain region and performing a low temperature thermal process.

    摘要翻译： 一种形成半导体器件的晶体管的方法，包括形成第一和第二导电类型的沟道层的步骤，进行高温热处理以形成稳定的沟道层并形成具有超陡逆向的外延沟道结构 通过生长未掺杂的硅外延层，用氢处理所得结构的整个表面，通过在稳定的沟道层上生长未掺杂的硅外延层，形成外延沟道结构，在外延沟道上形成栅极绝缘膜和栅电极 结构，重新氧化栅极绝缘膜，以修复栅极绝缘膜的损坏部分; 以及形成源极/漏极区域并进行低温热处理。

    Method for fabricating semiconductor device
    3.
    发明授权
    Method for fabricating semiconductor device 失效
    制造半导体器件的方法

    公开(公告)号：US06767808B2

    公开(公告)日：2004-07-27

    申请号：US10331579

    申请日：2002-12-31

    申请人： Chang-Woo Ryoo

    发明人： Chang-Woo Ryoo

    IPC分类号： H01L2104

    CPC分类号： H01L21/324 ,  H01L21/2658 ,  H01L29/1033 ,  H01L29/66575 ,  H01L29/78

    摘要： A method for forming a p-channel metal-oxide semiconductor(PMOS) device is suitable for reducing the width of change of a threshold voltage by preventing a deterioration of a uniformity of dopants due to out diffusion and segregation of the dopants implanted into channel regions. The method includes the steps of: forming a channel region below a surface of a semiconductor substrate; activating dopants implanted into the channel region through a first annealing process performed twice by rising temperature velocities different to each other; forming a gate oxidation layer and a gate electrode on the semiconductor substrate subsequently; forming a source/drain regions at both sides of the gate electrode in the semiconductor substrate; and activating dopants implanted into the source/drain regions through a second annealing process performed at the same conditions of the first annealing process.

    摘要翻译： 用于形成p沟道金属氧化物半导体（PMOS）器件的方法适用于通过防止由于注入到沟道区中的掺杂剂的扩散和偏析导致的掺杂剂的均匀性的劣化来减小阈值电压的变化的宽度 。 该方法包括以下步骤：在半导体衬底的表面下形成沟道区; 通过相互不同的升高的温度进行两次进行的第一退火处理来激活注入到沟道区的掺杂剂; 随后在半导体衬底上形成栅极氧化层和栅电极; 在半导体衬底中的栅电极的两侧形成源/漏区; 以及通过在第一退火工艺的相同条件下进行的第二退火工艺激活注入到源/漏区的掺杂剂。

    Method of selective epitaxial growth for semiconductor devices
    4.
    发明授权
    Method of selective epitaxial growth for semiconductor devices 失效
    半导体器件的选择性外延生长方法

    公开(公告)号：US06541355B2

    公开(公告)日：2003-04-01

    申请号：US10034392

    申请日：2001-12-28

    申请人： Sung Jae Joo ,  Chang Woo Ryoo

    发明人： Sung Jae Joo ,  Chang Woo Ryoo

    IPC分类号： H01L2120

    CPC分类号： C30B29/06 ,  C30B25/02 ,  C30B29/08 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02639

    摘要： A method of selective epitaxial growth for a semiconductor device is disclosed. By employing a hydrogen gas as a selectivity promoting gas in addition to a chlorine gas conventionally used, the method can guarantee the selectivity of epitaxial growth and further increase the growth rate of an epitaxial layer. The method begins with loading a semiconductor substrate into a reaction chamber. The substrate has a mask layer, which is selectively formed thereon to define a first portion exposed beyond the mask layer and a second portion covered by the mask layer. Next, a source gas is supplied into the reaction chamber so that the source gas is adsorbed on the first portion and thus the epitaxial layer is selectively formed on the first portion. Then, the selectivity promoting gas including the H2 gas into the reaction chamber, whereby any nucleus of semiconductor material is removed from the mask layer. Thereafter, the source gas and the selectivity promoting gas are sequentially and repeatedly supplied until the semiconductor epitaxial layer is grown to a desired thickness.

    摘要翻译： 公开了一种用于半导体器件的选择性外延生长的方法。 除了常规使用的氯气之外，通过使用氢气作为选择性促进气体，该方法可以保证外延生长的选择性并进一步增加外延层的生长速率。 该方法开始于将半导体衬底加载到反应室中。 衬底具有掩模层，其被选择性地形成在其上以限定暴露于掩模层外的第一部分和被掩模层覆盖的第二部分。 接下来，将源气体供应到反应室中，使得源气体吸附在第一部分上，因此在第一部分上选择性地形成外延层。 然后，将包含H 2气体的选择性促进气体引入反应室，由此从掩模层除去半导体材料的任何核。 此后，依次重复地供给源气体和选择性促进气体，直到半导体外延层生长至期望的厚度为止。

    Method for fabricating CMOS transistor
    9.
    发明授权
    Method for fabricating CMOS transistor 有权
    制造CMOS晶体管的方法

    公开(公告)号：US06767780B2

    公开(公告)日：2004-07-27

    申请号：US10331590

    申请日：2002-12-31

    申请人： Yong-Sun Sohn ,  Chang-Woo Ryoo ,  Jeong-Youb Lee

    发明人： Yong-Sun Sohn ,  Chang-Woo Ryoo ,  Jeong-Youb Lee

    IPC分类号： H01L218238

    CPC分类号： H01L29/6659 ,  H01L21/26586 ,  H01L21/823807 ,  H01L21/823892 ,  H01L27/0921 ,  H01L29/1083 ,  H01L29/7833

    摘要： A method for fabricating a CMOS transistor is disclosed. The present invention provides a method for producing a CMOS transistor having enhanced performance since a short channel characteristic and operation power can be controlled by the duplicate punch stop layer of the pMOS region and the operation power of the nMOS is also controlled by dopant concentration of the duplicated LDD region combined by the first LDD region and the second LDD region.

    摘要翻译： 公开了一种制造CMOS晶体管的方法。 本发明提供了一种具有增强性能的CMOS晶体管的制造方法，因为可以通过pMOS区域的复制冲击阻挡层控制短沟道特性和操作功率，并且nMOS的操作功率也由掺杂剂浓度 由第一LDD区域和第二LDD区域组合的复制LDD区域。

    Method of manufacturing a semiconductor device
    10.
    发明授权
    Method of manufacturing a semiconductor device 有权
    制造半导体器件的方法

    公开(公告)号：US06255153B1

    公开(公告)日：2001-07-03

    申请号：US09221286

    申请日：1998-12-23

    申请人： Chang Woo Ryoo

    发明人： Chang Woo Ryoo

    IPC分类号： H01L218238

    CPC分类号： H01L21/823892 ,  H01L27/0928

    摘要： The present invention is directed to a method of manufacturing a semiconductor device having a triple-well structure, comprising the steps of: forming a first pattern of a semiconductor substrate having a first N-well forming area, a R-well forming area, a second N-well forming area and a P-well forming area; forming a first layer within the substrate at a predetermining depth by implanting a N-type impurity ion using the first pattern as a mask; forming a bottom N-well within the substrate at a predetermined depth by implanting a N-type impurity ion using the first pattern as a mask; removing the first pattern; forming a second pattern on the substrate; forming a first lateral N-well and a second lateral N-well by implanting a N-type impurity ion using the second pattern as a mask, and portions of the first and second lateral N-wells overlap with opposite edge portions of the bottom N-well, thereby forming a N-well; removing the second pattern; forming a third pattern on the substrate; forming a second defect layer within the substrate at a predetermined depth by implanting a P-type impurity ion using the third pattern as a mask; forming a fourth pattern on the substrate; forming a R-well by implanting a P-type impurity ion using the fourth pattern as a mask; removing the fourth pattern; and performing rapid head treatment.

    摘要翻译： 本发明涉及一种制造具有三阱结构的半导体器件的方法，包括以下步骤：形成具有第一N阱形成区域，R阱形成区域的半导体衬底的第一图案， 第二N阱形成区域和P阱形成区域; 通过使用第一图案作为掩模注入N型杂质离子，以预定深度在衬底内形成第一层; 通过使用第一图案作为掩模注入N型杂质离子，在预定深度的衬底内形成底部N阱; 去除第一个模式; 在衬底上形成第二图案; 通过使用第二图案作为掩模注入N型杂质离子形成第一横向N阱和第二横向N阱，并且第一和第二横向N阱的部分与底部N的相对边缘部分重叠 由此形成N阱; 去除第二模式; 在基板上形成第三图案; 通过使用第三图案作为掩模注入P型杂质离子，在预定深度的衬底内形成第二缺陷层; 在基板上形成第四图案; 通过使用第四图案作为掩模注入P型杂质离子形成R阱; 去除第四种模式; 并进行快速头部治疗。