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    Electronic systems and apparatus for recognising printed characters
    94.
    发明授权
    Electronic systems and apparatus for recognising printed characters 失效
    用于识别打印字符的电子系统和装置

    公开(公告)号：US3534332A

    公开(公告)日：1970-10-13

    申请号：US3534332D

    申请日：1966-11-14

    Applicant: NAT RES DEV

    Inventor： PARKS JOHN R

    IPC: G06K9/80 ,  G06K9/12

    CPC classification number: G06K9/80 ,  G06K9/40 ,  G06K9/52 ,  G06K9/64

    Abstract: 1,170,234. Character recognition. NATIONAL RESEARCH DEVELOPMENT CORP. 14 Nov., 1966 [12 Nov., 1965], No. 48171/65. Heading G4R. Character recognition apparatus multiplies together relatively delayed versions of an analogue signal waveform derived from a raster scan of the character, to obtain analogue shape feature indicating signals which are then combined to identify the character such that a given character is indicated only if the correct shape features occur in the correct physical disposition relative to each other. Referring to Figs. 4, 5, the waveform from a raster of vertical scans of the character to be identified is amplified logarithmically at 14 and applied to delay lines DL1-DL9 as shown. Each delay line DL1-DL4 has a delay of four scan lines and each delay line DL5-DL9 of one scan line. Tappings on lines DL5-DL9 feed adders ADR1-ADRn to recognize geometric features, e.g. straight and curved lines in various orientations. The adders feed " blur " filters BF1-BFn via antilog amplifiers ALA1- ALAn. The blur filters are low-pass filters for broadening the signal peaks to allow for circuit noise and variations in ink density. The blur filters feed weighting and combining networks CNl-CNn, one per possible character, via delays DM1 &c. which serve to bring feature signals derived from different parts of the character to the appropriate weighting and combining network simultaneously. The largest network output is selected as identifying the character. In a modification (Figs. 6, 7, not shown), blurring and combining is done in delay lines, one per possible character. Each delay line receives the outputs of several of the antilog amplifiers of Fig. 4 which are applied to respective positions along its length. Three taps, one scan time apart, on each line feed a summer respective to the line (to provide blurring between adjacent scans). Blurring along each scan is provided by limiting the response bandwidth of the delay lines. The summer outputs are gated (except during scan fly-back) to respective peak detectors, the largest output of which is selected to identify the character under control of a validity check circuit which can also produce a reject signal. In addition, the largest of the gated summer outputs is filtered to remove transients, then differentiated before being passed to two Schmitt triggers which produce outputs on positive-to-negative and negative-to-positive zero-crossings respectively. These outputs indicate the reaching of the best time to sample the previous signals to identify the character, and the " boundary " between successive characters respectively. The validity check circuit utilizes pulse lengtheners, storage triggers and logic circuitry to perform checks on the relative timing of these signals in dependence on predetermined maximum and minimum character widths. The delay lines of Fig. 5 may be eliminated by suitable choice of the tappings on those of Fig. 4.

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