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公开(公告)号：US10269671B2
公开(公告)日：2019-04-23
申请号：US15647206
申请日：2017-07-11
发明人： Hung-Hsin Hsu , Nan-Chun Lin
IPC分类号： H01L23/31 , H01L23/00 , H01L23/498 , H01L23/538 , H01L27/146 , H01L21/56
摘要： A manufacturing method of a package structure includes at least the following steps. A plurality of conductive connectors are formed on a circuit layer. The circuit layer includes a central region and a peripheral region electrically connected to the central region. A chip is disposed on the central region of the circuit layer. The chip includes an active surface at a distance from the circuit layer and a sensing area on the active surface. An encapsulant is formed on the circuit layer to encapsulate the chip and the conductive connectors. A redistribution layer is formed on the encapsulant to electrically connect the chip and the conductive connectors. The redistribution layer partially covers the chip and includes a window corresponding to the sensing area of the chip. A package structure is also provided.
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公开(公告)号：US10249573B2
公开(公告)日：2019-04-02
申请号：US15461465
申请日：2017-03-16
发明人： Ting-Feng Su , Chia-Jen Chou
IPC分类号： H01L23/00 , H01L23/538 , H01L21/56 , H01L21/48 , H01L23/373 , H01L23/31
摘要： A semiconductor device package has a die, a pattern of dielectric material formed on an active surface of the die, a plurality of metal contacts electrically connected to the die and surrounded by the pattern, a mold compound formed around the pattern, the die and the metal contacts, and a redistribution layer formed on a grinded surface of the mold compound and electrically connected to the metal contacts. The dielectric material has a young's modulus lower than a young's modulus of the mold compound, and the dielectric material has a coefficient of thermal expansion lower than a coefficient of thermal expansion of the mold compound.
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公开(公告)号：US20190096866A1
公开(公告)日：2019-03-28
申请号：US15715169
申请日：2017-09-26
发明人： Ching-Ming Hsu , Wen-Hsiung Chang , Po-Wei Yeh , Yun-Hsin Yeh
摘要： A semiconductor package including a first semiconductor chip, a plurality of first conductors, a first conductive pattern electrically connected to the first conductors, a second semiconductor chip disposed on the first semiconductor chip, and an encapsulant on the first conductive pattern and laterally encapsulating the second semiconductor chip. The first semiconductor chip electrically connected to the first conductors includes a sensing area on a first active surface, a first back surface and a plurality of through holes extending form the first back surface towards the first active surface. The second semiconductor chip including a second active surface facing towards the first back surface electrically connects the first semiconductor chip through the first conductors in the through holes and the first conductive pattern on the first back surface. A manufacturing method of a semiconductor package is also provided.
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公开(公告)号：US20190013283A1
公开(公告)日：2019-01-10
申请号：US15646055
申请日：2017-07-10
IPC分类号： H01L23/00 , H01L21/56 , H01L23/31 , H01L25/065 , H01L21/683
摘要： A method of forming a Fan-Out Wafer Level semiconductor device includes forming only a plurality of metal bonding pads on a glass carrier. Electrode pads of a semiconductor chip are coupled to the plurality of metal bonding pads. The semiconductor chip and the plurality of metal bonding pads are encapsulated with a molding compound. The glass carrier can then be removed to expose a surface of the FOWLP structure. A redistribution layer is then formed on the exposed surface of the FOWLP structure. At least one metal trace within the redistribution layer is in electrical contact with the plurality of metal bonding pads. Solder balls may be mounted on the redistribution layer to provide electrical contact between the solder balls and the electrode pads of the semiconductor chip.
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公开(公告)号：US10177077B2
公开(公告)日：2019-01-08
申请号：US15671156
申请日：2017-08-08
发明人： Chi-Liang Pan , Ting-Feng Su
IPC分类号： H01L23/482 , H01L23/00 , H01L23/31
摘要： A chip structure including a chip and a redistribution layer is provided. The chip includes a plurality of pads. The redistribution layer includes a dielectric layer and a plurality of conductive traces. The dielectric layer is disposed on the chip and has a plurality of contact windows located above the pads. The conductive traces are located on the dielectric layer and are electrically coupled to the pads through the contact windows. At least one of the conductive traces includes a body and at least one protrusion coupled to the body, and the at least one protrusion is coupled to an area of the body other than where the contact windows are coupled to on the body.
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公开(公告)号：US10170458B2
公开(公告)日：2019-01-01
申请号：US15782862
申请日：2017-10-13
发明人： Chi-An Wang , Hung-Hsin Hsu
IPC分类号： H01L23/00 , H01L25/00 , H01L21/48 , H01L23/31 , H01L23/498 , H01L25/10 , H01L23/49 , H01L23/50 , H01L21/56 , H01L23/538 , H01L25/065 , H01L23/04 , H01L23/433
摘要： A manufacturing method of a POP structure including at least the following steps is provided. A first package structure is formed and a second package structure is formed on the first package structure. The first package structure includes a circuit carrier and a die disposed on the circuit carrier. Forming the first package structure includes providing a conductive interposer on the circuit carrier, encapsulating the conductive interposer by an encapsulant and removing a portion of the encapsulant and the plate of the conductive interposer. The conductive interposer includes a plate, a plurality of conductive pillars and a conductive protrusion respectively extending from the plate to the circuit carrier and the die. The conductive protrusion disposed on the die, and the conductive pillars are electrically connected to the circuit carrier. The second package structure is electrically connected to the first package structure through the conductive interposer.
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公开(公告)号：US10157828B2
公开(公告)日：2018-12-18
申请号：US15599477
申请日：2017-05-19
发明人： Hung-Hsin Hsu , Nan-Chun Lin
摘要： A chip package structure includes a semiconductor component, a plurality of conductive pillars, an encapsulant and a redistribution layer. The semiconductor component includes a plurality of pads. The conductive pillars are disposed on the pads, wherein each of the conductive pillars is a solid cylinder including a top surface and a bottom surface, and a diameter of the top surface is substantially the same as a diameter of the bottom surface. The encapsulant encapsulates the semiconductor component and the conductive pillars, wherein the encapsulant exposes the top surface of each of the conductive pillars. The redistribution layer is disposed on the encapsulant and electrically connected to the conductive pillars.
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公开(公告)号：US10121736B2
公开(公告)日：2018-11-06
申请号：US15876210
申请日：2018-01-22
发明人： Kuo-Ting Lin , Chia-Wei Chang
IPC分类号： H01L23/498 , H01L23/00 , H01L21/48 , H01L21/56 , H01L25/065 , H01L23/538
摘要： A method of fabricating a packaging layer of an fan-out chip package comprising: disposing a chip on a temporary carrier; forming an encapsulation on the temporary carrier to encapsulate the chip; grinding the encapsulation and the chip to form a back surface of the chip and a back surface of the encapsulation; debonding the encapsulation and the chip from the temporary carrier; forming a first passivation layer on the active surface of the chip and the peripheral surface of the encapsulation; patterning the first passivation layer to form fan-in openings and fan-out openings on the first passivation layer; forming a redistribution layer on the first passivation layer; forming a second passivation layer on the first passivation layer and the redistribution wiring layer; forming vertical connectors within the encapsulation to correspondingly couple to the fan-out pads; and disposing a plurality of dummy terminals on the dummy pattern.
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99.发明申请公开(公告)号：US20180315674A1
公开(公告)日：2018-11-01
申请号：US15497219
申请日：2017-04-26
发明人： Ming-Chih Chen , Hsien-Wen Hsu , Yuan-Fu Lan , Hung-Hsin Hsu
IPC分类号： H01L23/043 , H01L23/06 , H01L23/31 , H01L21/82 , H01L23/48 , H01L23/498 , H01L23/00
CPC分类号： H01L23/043 , H01L21/82 , H01L23/06 , H01L23/3114 , H01L23/3128 , H01L23/315 , H01L23/481 , H01L23/49827 , H01L24/10 , H01L24/11 , H01L2221/1068 , H01L2224/10 , H01L2224/11
摘要： A package structure may include a one-piece metal carrier, a die, a mold layer and a redistribution layer. The one-piece metal carrier may include a bottom portion and a first supporting structure, and the one-piece metal carrier may have a recess defined by the bottom portion and the first supporting structure. The die may be disposed in the recess of the one-piece metal carrier, and the die may have a plurality of conductive bumps. The mold layer may be formed to encapsulate the die. The mold layer may expose a portion of each of the plurality of conductive bumps and a portion of the first supporting structure. The redistribution layer may be disposed on the mold layer and electrically connected to the plurality of conductive bumps.
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公开(公告)号：US20180269160A1
公开(公告)日：2018-09-20
申请号：US15461465
申请日：2017-03-16
发明人： Ting-Feng Su , Chia-Jen Chou
IPC分类号： H01L23/00 , H01L23/31 , H01L23/538 , H01L23/373 , H01L21/56 , H01L21/48
CPC分类号： H01L23/562 , H01L21/4853 , H01L21/4857 , H01L21/561 , H01L21/563 , H01L21/565 , H01L21/568 , H01L23/3114 , H01L23/3128 , H01L23/315 , H01L23/3737 , H01L23/5383 , H01L23/5386
摘要： A semiconductor device package has a die, a pattern of dielectric material formed on an active surface of the die, a plurality of metal contacts electrically connected to the die and surrounded by the pattern, a mold compound formed around the pattern, the die and the metal contacts, and a redistribution layer formed on a grinded surface of the mold compound and electrically connected to the metal contacts. The dielectric material has a young's modulus lower than a young's modulus of the mold compound, and the dielectric material has a coefficient of thermal expansion lower than a coefficient of thermal expansion of the mold compound.
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