公开(公告)号：US10469058B1

公开(公告)日：2019-11-05

申请号：US15990944

申请日：2018-05-29

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Guenole Lallement ,  Fady Abouzeid

IPC: H03K3/013 ,  H03K3/012 ,  H03K3/03

Abstract: A multi-stage ring oscillator generates an output clock signal having a frequency which is dependent on a digitally leakage current that is applied to each stage of the multi-stage ring oscillator. A magnitude of a leakage current sourced by each digitally controlled leakage current source is set by a control circuit in response to a selection signal. A calibration circuit processes a reference clock signal and the output clock signal generated by the multi-stage ring oscillator to make adjustment to the selection signal which drives a locking of a frequency of the output clock signal to a desired frequency.

公开(公告)号：US10451670B2

公开(公告)日：2019-10-22

申请号：US15378663

申请日：2016-12-14

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sylvain Clerc

IPC: G01R31/28 ,  G01R31/30 ,  G01R31/317 ,  H03K5/133 ,  H03K19/003

Abstract: A device for monitoring a critical path of an integrated circuit includes a replica of the critical path formed by sequential elements mutually separated by delay circuits that are programmable though a corresponding main multiplexer. A control circuit controls delay selections made by each main multiplexer. A sequencing module operates to sequence each sequential element using a main clock signal by delivering, in response to a main clock signal, respectively to the sequential elements, secondary clock signals that are mutually time shifted in such a manner as to take into account the propagation time inherent to the main multiplexer.

公开(公告)号：US10447230B2

公开(公告)日：2019-10-15

申请号：US15653014

申请日：2017-07-18

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics S.A.

Inventor： Frédéric Gianesello ,  Romain Pilard ,  Cédric Durand

IPC: H01F27/28 ,  H03H7/42 ,  H01F27/38 ,  H01L23/522 ,  H01F27/29 ,  H01F27/40 ,  H04W88/02

Abstract: A transformer of the balanced-unbalanced type includes a primary inductive circuit and a secondary inductive circuit housed inside an additional inductive winding connected in parallel to the terminals of the secondary circuit and inductively coupled with the primary circuit and the secondary circuit.

公开(公告)号：US10446535B2

公开(公告)日：2019-10-15

申请号：US15137201

申请日：2016-04-25

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Alexandre Ayres ,  Bertrand Borot

IPC: H01L23/48 ,  H01L27/02 ,  G06F17/50 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/088

Abstract: A three-dimensional integrated structure is formed by a first substrate with first components oriented in a first direction and a second substrate with second components oriented in a second direction. An interconnection level includes electrically conducting tracks that run in a third direction. One of the second direction and third direction forms a non-right and non-zero angle with the first direction. An electrical link formed by at least one of the electrically conducting tracks electrically connected two points of the first or of the second components.

公开(公告)号：US20190312170A1

公开(公告)日：2019-10-10

申请号：US16222542

申请日：2018-12-17

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Francois ROY

IPC: H01L31/113 ,  H01L27/146 ,  H01L31/0224

Abstract: A semiconductor substrate doped with a first doping type is positioned adjacent an insulated gate electrode that is biased by a gate voltage. A first region within the semiconductor substrate is doped with the first doping type and biased with a bias voltage. A second region within the semiconductor substrate is doped with a second doping type that is opposite the first doping type. Voltage application produces an electrostatic field within the semiconductor substrate causing the formation of a fully depleted region within the semiconductor substrate. The fully depleted region responds to absorption of a photon with an avalanche multiplication that produces charges that are collected at the first and second regions.

公开(公告)号：US10418486B2

公开(公告)日：2019-09-17

申请号：US15976452

申请日：2018-05-10

Applicant: STMicroelectronics (Crolles 2) SAS ,  Commissariat A L'Energie Atomique et aux Energies Alternatives

Inventor： Remy Berthelon ,  Francois Andrieu

IPC: H01L29/78 ,  H01L21/8238 ,  H01L21/84 ,  H01L27/02 ,  H01L27/12 ,  H01L27/092 ,  H01L21/762 ,  H01L29/786

Abstract: Longitudinal trenches extend between and on either side of first and second side-by-side strips. Transverse trenches extend from one edge to another edge of the first strip to define tensilely strained semiconductor slabs in the first strip, with the second strip including portions that are compressively strained in the longitudinal direction and/or tensilely strained in the transverse direction. In the first strip, N-channel MOS transistors are located inside and on top of the semiconductor slabs. In the second strip, P-channel MOS transistors are located inside and on top of the portions.

公开(公告)号：US10403682B2

公开(公告)日：2019-09-03

申请号：US15968474

申请日：2018-05-01

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pierre Morin ,  Philippe Brun ,  Laurent-Luc Chapelon

IPC: H01L27/24 ,  H01L45/00 ,  H01L23/528 ,  H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/768

Abstract: A phase-change memory includes a strip of phase-change material that is coated with a conductive strip and surrounded by an insulator. The strip of phase-change material has a lower face in contact with tips of a resistive element. A connection network composed of several levels of metallization coupled with one another by conducting vias is provided above the conductive strip. At least one element of a lower level of the metallization is in direct contact with the upper surface of the conductive strip.

公开(公告)号：US10397503B2

公开(公告)日：2019-08-27

申请号：US15376792

申请日：2016-12-13

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Pierre Emmanuel Marie Malinge ,  Frederic Lalanne

IPC: H04N5/359 ,  H04N5/355 ,  H04N5/3745

Abstract: A photodiode produces photogenerated charges in response to exposure to light. An integration period collects the photogenerated charges. Collected photogenerated charges in excess of an overflow threshold are passed to an overflow sense node. Remaining collected photogenerated charges are passed to a sense node. A first signal representing the overflow photogenerated charges is read from the overflow sense node. A second signal representing the remaining photogenerated charges is read from the sense node.

公开(公告)号：US10393965B2

公开(公告)日：2019-08-27

申请号：US16148535

申请日：2018-10-01

Applicant: STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Nicolas Michit ,  Patrick Le Maitre

IPC: G02B6/293 ,  H04Q11/00

Abstract: A photonic interconnection elementary switch is integrated in an optoelectronic chip/The switch includes first and second linear optical waveguides which intersect to form a first intersection. Two first photonic redirect ring resonators are respectively coupled to the first and second optical waveguides. Two second photonic redirect ring resonators are respectively coupled to the first and second optical waveguides. A third linear optical waveguide is coupled to one of the first ring resonators and one of the second ring resonators. A fourth linear optical waveguide is coupled to another of the first resonators and to another of the second ring resonators. A base switch, complex switch, and photonic interconnection network integrated in an optoelectronic chip, include at least two of the photonic interconnection elementary switches.

公开(公告)号：US10381394B2

公开(公告)日：2019-08-13

申请号：US15813414

申请日：2017-11-15

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Nicolas Hotellier

IPC: H01L27/146 ,  H01L31/18 ,  H01L21/768

Abstract: An electronic component includes a semiconductor layer having a first surface coated with a first insulating layer and a second surface coated with an interconnection structure. A laterally insulated conductive pin extends through the semiconductor layer from a portion of conductive layer of the interconnection structure all the way to a contact pad arranged at the level of the first insulating layer.