公开(公告)号：US09847365B2

公开(公告)日：2017-12-19

申请号：US14960018

申请日：2015-12-04

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Nicolas Hotellier

IPC: H01L27/146 ,  H01L31/18 ,  H01L21/768

CPC classification number: H01L27/14636 ,  H01L21/76898 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14687 ,  H01L27/14689 ,  H01L31/1892 ,  H01L2224/05

Abstract: An electronic component includes a semiconductor layer having a first surface coated with a first insulating layer and a second surface coated with an interconnection structure. A laterally insulated conductive pin extends through the semiconductor layer from a portion of conductive layer of the interconnection structure all the way to a contact pad arranged at the level of the first insulating layer.

公开(公告)号：US11183468B2

公开(公告)日：2021-11-23

申请号：US15638883

申请日：2017-06-30

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Petitdidier ,  Nicolas Hotellier ,  Raul Andres Bianchi ,  Alexis Farcy ,  Benoît Froment

IPC: H01L23/00 ,  H01L49/02 ,  H01L23/498 ,  H01L23/64 ,  H01L23/58 ,  H01L23/48 ,  H01L21/768 ,  H01L21/311 ,  H01L23/29 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H03K3/3565

Abstract: A semiconductor chip includes at least two insulated vias passing through the chip from the front face to the rear face in which, on the side of the rear face, the vias are connected to one and the same conducting strip and, on the side of the front face, each via is separated from a conducting pad by a layer of a dielectric.

公开(公告)号：US12087708B2

公开(公告)日：2024-09-10

申请号：US17451718

申请日：2021-10-21

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Petitdidier ,  Nicolas Hotellier ,  Raul Andres Bianchi ,  Alexis Farcy ,  Benoit Froment

IPC: H01L23/00 ,  H01L21/311 ,  H01L21/768 ,  H01L23/29 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L23/522 ,  H01L23/528 ,  H01L23/58 ,  H01L23/64 ,  H03K3/3565

CPC classification number: H01L23/576 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/49855 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/57 ,  H01L23/573 ,  H01L23/585 ,  H01L23/642 ,  H03K3/3565 ,  H01L23/293

Abstract: A method for fabricating a semiconductor chip includes forming a plurality of conducting pads at a front face of a substrate, thinning a rear face of the substrate, etching openings under each conducting pad from the rear face, depositing a layer of a dielectric on walls and a bottom of the openings, forming a conducting material in the openings, and forming a conducting strip on the rear face. The conducting strip is electrically connected to the conducting material of each of the openings. The etching is stopped when the respective conducting pad is reached.

公开(公告)号：US10381394B2

公开(公告)日：2019-08-13

申请号：US15813414

申请日：2017-11-15

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Nicolas Hotellier

IPC: H01L27/146 ,  H01L31/18 ,  H01L21/768

Abstract: An electronic component includes a semiconductor layer having a first surface coated with a first insulating layer and a second surface coated with an interconnection structure. A laterally insulated conductive pin extends through the semiconductor layer from a portion of conductive layer of the interconnection structure all the way to a contact pad arranged at the level of the first insulating layer.

公开(公告)号：US20180083060A1

公开(公告)日：2018-03-22

申请号：US15813414

申请日：2017-11-15

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Nicolas Hotellier

IPC: H01L27/146 ,  H01L31/18 ,  H01L21/768

CPC classification number: H01L27/14636 ,  H01L21/76898 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14687 ,  H01L27/14689 ,  H01L31/1892 ,  H01L2224/05

Abstract: An electronic component includes a semiconductor layer having a first surface coated with a first insulating layer and a second surface coated with an interconnection structure. A laterally insulated conductive pin extends through the semiconductor layer from a portion of conductive layer of the interconnection structure all the way to a contact pad arranged at the level of the first insulating layer.

公开(公告)号：US20180061781A1

公开(公告)日：2018-03-01

申请号：US15638883

申请日：2017-06-30

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Sebastien Petitdidier ,  Nicolas Hotellier ,  Raul Andres Bianchi ,  Alexis Farcy ,  Benoît Froment

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L23/29 ,  H01L21/311 ,  H01L21/768 ,  H03K3/3565

CPC classification number: H01L23/576 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/291 ,  H01L23/293 ,  H01L23/3171 ,  H01L23/481 ,  H01L23/49855 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/57 ,  H01L23/573 ,  H01L23/585 ,  H01L23/642 ,  H03K3/3565

Abstract: A semiconductor chip includes at least two insulated vias passing through the chip from the front face to the rear face in which, on the side of the rear face, the vias are connected to one and the same conducting strip and, on the side of the front face, each via is separated from a conducting pad by a layer of a dielectric.

公开(公告)号：US09648724B2

公开(公告)日：2017-05-09

申请号：US14956512

申请日：2015-12-02

Applicant: STMICROELECTRONICS (CROLLES 2) SAS ,  STMICROELECTRONICS SA

Inventor： Nicolas Hotellier ,  François Guyader ,  Vincent Fiori ,  Richard Fournel ,  Frédéric Gianesello

IPC: H05K1/02 ,  H05K1/11 ,  H05K1/18 ,  H05K3/00 ,  H01L21/762 ,  H01L21/764

CPC classification number: H05K1/0216 ,  H01L21/762 ,  H01L21/7624 ,  H01L21/764 ,  H01L24/03 ,  H01L24/05 ,  H01L29/0657 ,  H01L2224/02166 ,  H01L2224/04042 ,  H01L2924/00014 ,  H05K1/111 ,  H05K1/181 ,  H05K3/0011 ,  H01L2224/05599

Abstract: An electronic device has a rear plate that includes a substrate rear layer, a substrate front layer and a dielectric intermediate layer between the substrate rear and front layers. An electronic structure is on the substrate front layer and includes electronic components and electrical connections. The substrate rear layer includes a solid local region and a hollowed-out local region. The hollowed-out local region extends over all of the substrate rear layer. The substrate rear layer does not cover at least one local zone of the dielectric intermediate layer corresponding to the hollowed-out local region.

公开(公告)号：US20160372510A1

公开(公告)日：2016-12-22

申请号：US14960018

申请日：2015-12-04

Applicant: STMicroelectronics (Crolles 2) SAS

Inventor： Nicolas Hotellier

IPC: H01L27/146

CPC classification number: H01L27/14636 ,  H01L21/76898 ,  H01L27/1464 ,  H01L27/14643 ,  H01L27/14687 ,  H01L27/14689 ,  H01L31/1892 ,  H01L2224/05

Abstract: An electronic component includes a semiconductor layer having a first surface coated with a first insulating layer and a second surface coated with an interconnection structure. A laterally insulated conductive pin extends through the semiconductor layer from a portion of conductive layer of the interconnection structure all the way to a contact pad arranged at the level of the first insulating layer.

Abstract translation: 电子部件包括具有涂覆有第一绝缘层的第一表面和涂覆有互连结构的第二表面的半导体层。 横向绝缘的导电针从互连结构的导电层的一部分延伸穿过半导体层到布置在第一绝缘层的层的接触焊盘。