-
公开(公告)号：US10403682B2
公开(公告)日：2019-09-03
申请号：US15968474
申请日：2018-05-01
Applicant: STMicroelectronics (Crolles 2) SAS
Inventor： Pierre Morin , Philippe Brun , Laurent-Luc Chapelon
IPC: H01L27/24 , H01L45/00 , H01L23/528 , H01L23/522 , H01L23/532 , H01L21/02 , H01L21/768
Abstract: A phase-change memory includes a strip of phase-change material that is coated with a conductive strip and surrounded by an insulator. The strip of phase-change material has a lower face in contact with tips of a resistive element. A connection network composed of several levels of metallization coupled with one another by conducting vias is provided above the conductive strip. At least one element of a lower level of the metallization is in direct contact with the upper surface of the conductive strip.
-
公开(公告)号：US12232435B2
公开(公告)日：2025-02-18
申请号：US18130184
申请日：2023-04-03
Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Rousset) SAS
Inventor： Franck Arnaud , David Galpin , Stephane Zoll , Olivier Hinsinger , Laurent Favennec , Jean-Pierre Oddou , Lucile Broussous , Philippe Boivin , Olivier Weber , Philippe Brun , Pierre Morin
Abstract: An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.
-
公开(公告)号：US11653577B2
公开(公告)日：2023-05-16
申请号：US17112842
申请日：2020-12-04
Applicant: STMicroelectronics (Crolles 2) SAS , Commissariat A L'Energie Atomique Et Aux Energies Alternatives
Inventor： Jean-Philippe Reynard , Sylvie Del Medico , Philippe Brun
CPC classification number: H01L45/16 , H01L27/222 , H01L27/24 , H01L43/02 , H01L43/12 , H01L45/06 , H01L45/1233
Abstract: A method for manufacturing an interconnection structure for an integrated circuit is provided. The integrated circuit includes a first insulating layer, a second insulating layer, and a third insulating layer. Electrical contacts pass through the first insulating layer, and a component having an electrical contact region is located in the second insulating layer. The method includes etching a first opening in the third layer, vertically aligned with the contact region. A fourth insulating layer is deposited to fill in the opening, and a second opening is etched to the contact region by passing through the opening in the third insulating layer. A metal level is formed by filling in the second opening with a metal.
-
Patent Agency Ranking
公开(公告)号：US12048257B2
公开(公告)日：2024-07-23
申请号：US18296331
申请日：2023-04-05
Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES , STMicroelectronics (Crolles 2) SAS
Inventor： Jean-Philippe Reynard , Sylvie Del Medico , Philippe Brun
CPC classification number: H10N70/011 , H10B61/00 , H10B63/00 , H10N50/01 , H10N50/80 , H10N70/231 , H10N70/826
Abstract: A method for manufacturing an interconnection structure for an integrated circuit is provided. The integrated circuit includes a first insulating layer, a second insulating layer, and a third insulating layer. Electrical contacts pass through the first insulating layer, and a component having an electrical contact region is located in the second insulating layer. The method includes etching a first opening in the third layer, vertically aligned with the contact region. A fourth insulating layer is deposited to fill in the opening, and a second opening is etched to the contact region by passing through the opening in the third insulating layer. A metal level is formed by filling in the second opening with a metal.
-
公开(公告)号：US12243895B2
公开(公告)日：2025-03-04
申请号：US17211739
申请日：2021-03-24
Applicant: STMICROELECTRONICS (CROLLES 2) SAS
Inventor： Thierry Berger , Marc Neyens , Audrey Vandelle Berthoud , Marc Guillermet , Philippe Brun
IPC: H01L27/146
Abstract: The present disclosure relates to a method for manufacturing a pixel by: depositing an insulating layer on an exposed face of an interconnect structure of an integrated circuit, the interconnect structure having a conductive element flush with said exposed face; etching an opening passing through the insulating layer to the conductive element; depositing an electrode layer on and in contact with the conductive element and the insulating layer; defining an electrode by removing, by etching, part of the electrode layer resting on the insulating layer; and depositing a film configured to convert photons into electron-hole pairs when a ray at an operating wavelength of the pixel reaches the pixel.
-
公开(公告)号：US20230247919A1
公开(公告)日：2023-08-03
申请号：US18296331
申请日：2023-04-05
Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES , STMicroelectronics (Crolles 2) SAS
Inventor： Jean-Philippe REYNARD , Sylvie DEL MEDICO , Philippe Brun
CPC classification number: H10N70/011 , H10B61/00 , H10B63/00 , H10N50/01 , H10N50/80 , H10N70/231 , H10N70/826
Abstract: A method for manufacturing an interconnection structure for an integrated circuit is provided. The integrated circuit includes a first insulating layer, a second insulating layer, and a third insulating layer. Electrical contacts pass through the first insulating layer, and a component having an electrical contact region is located in the second insulating layer. The method includes etching a first opening in the third layer, vertically aligned with the contact region. A fourth insulating layer is deposited to fill in the opening, and a second opening is etched to the contact region by passing through the opening in the third insulating layer. A metal level is formed by filling in the second opening with a metal.
-
公开(公告)号：US11653582B2
公开(公告)日：2023-05-16
申请号：US16184246
申请日：2018-11-08
Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics (Grenoble 2) SAS , STMicroelectronics (Rousset) SAS
Inventor： Franck Arnaud , David Galpin , Stephane Zoll , Olivier Hinsinger , Laurent Favennec , Jean-Pierre Oddou , Lucile Broussous , Philippe Boivin , Olivier Weber , Philippe Brun , Pierre Morin
CPC classification number: H10N70/8616 , G11C13/0004 , G11C13/0069 , H10B63/30 , H10B63/80 , H10N70/011 , H10N70/021 , H10N70/231 , H10N70/826 , H10N70/8265 , H10N70/8413 , H10N70/882 , G11C2013/008
Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.
-
公开(公告)号：US20210175422A1
公开(公告)日：2021-06-10
申请号：US17112842
申请日：2020-12-04
Applicant: STMicroelectronics (Crolles 2) SAS , Commissariat A L'Energie Atomique Et Aux Energies Alternatives
Inventor： Jean-Philippe REYNARD , Sylvie DEL MEDICO , Philippe Brun
Abstract: A method for manufacturing an interconnection structure for an integrated circuit is provided. The integrated circuit includes a first insulating layer, a second insulating layer, and a third insulating layer. Electrical contacts pass through the first insulating layer, and a component having an electrical contact region is located in the second insulating layer. The method includes etching a first opening in the third layer, vertically aligned with the contact region. A fourth insulating layer is deposited to fill in the opening, and a second opening is etched to the contact region by passing through the opening in the third insulating layer. A metal level is formed by filling in the second opening with a metal.
-
-
-
-
-
-
-
Search Results
8
records
(took 0.012 seconds)
