公开(公告)号：US20120054449A1

公开(公告)日：2012-03-01

申请号：US12871164

申请日：2010-08-30

Applicant: Shiliang Hu ,  Youfeng Wu

Inventor： Shiliang Hu ,  Youfeng Wu

IPC: G06F12/08 ,  G06F12/00

CPC classification number: G06F12/0862 ,  G06F2212/1041 ,  G06F2212/502 ,  G06F2212/6024 ,  G06F2212/6026

Abstract: In one embodiment, the present invention includes a prefetching engine to detect when data access strides in a memory fall into a range, to compute a predicted next stride, to selectively prefetch a cache line using the predicted next stride, and to dynamically control prefetching. Other embodiments are also described and claimed.

Abstract translation: 在一个实施例中，本发明包括一种预取引擎，用于检测存储器中的数据访问步进何时落入一个范围内，以计算预测的下一步，以使用预测的下一步来选择性地预取高速缓存行，并且动态地控制预取。 还描述和要求保护其他实施例。

公开(公告)号：US20120016853A1

公开(公告)日：2012-01-19

申请号：US13246678

申请日：2011-09-27

Applicant: Cheng Wang ,  Youfeng Wu ,  Wei-Yu Chen ,  Bratin Saha ,  Ali Reza Adl-Tabatabai

Inventor： Cheng Wang ,  Youfeng Wu ,  Wei-Yu Chen ,  Bratin Saha ,  Ali Reza Adl-Tabatabai

IPC: G06F7/00

CPC classification number: G06F8/458 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3834 ,  G06F9/3859 ,  G06F9/3863 ,  G06F9/467

Abstract: A method and apparatus for efficient and consistent validation/conflict detection in a Software Transactional Memory (STM) system is herein described. A version check barrier is inserted after a load to compare versions of loaded values before and after the load. In addition, a global timestamp (GTS) is utilized to track a latest committed transaction. Each transaction is associated with a local timestamp (LTS) initialized to the GTS value at the start of a transaction. As a transaction commits it updates the GTS to a new value and sets versions of modified locations to the new value. Pending transactions compare versions determined in read barriers to their LTS. If the version is greater than their LTS indicating another transaction has committed after the pending transaction started and initialized the LTS, then the pending transaction validates its read set to maintain efficient and consistent transactional execution.

Abstract translation: 这里描述了用于在软件事务存储器（STM）系统中有效且一致的验证/冲突检测的方法和装置。 在加载之后插入版本检查障碍，以便在加载之前和之后比较加载值的版本。 此外，使用全局时间戳（GTS）来跟踪最近提交的事务。 每个事务与在事务开始时初始化为GTS值的本地时间戳（LTS）相关联。 作为事务提交，将GTS更新为新值，并将修改的位置的版本设置为新值。 待处理的交易将比较其在LTS阅读障碍中确定的版本。 如果版本大于其LTS，指示在挂起事务启动并初始化LTS之后另一个事务已经提交，则挂起的事务会验证其读取集合以保持有效且一致的事务执行。

公开(公告)号：US20110320781A1

公开(公告)日：2011-12-29

申请号：US12826287

申请日：2010-06-29

Applicant: Wei Liu ,  Youfeng Wu

Inventor： Wei Liu ,  Youfeng Wu

IPC: G06F9/312 ,  G06F12/02 ,  G06F12/08

CPC classification number: G06F9/3834 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3851 ,  G06F9/52

Abstract: In one embodiment, the present invention introduces a speculation engine to parallelize serial instructions by creating separate threads from the serial instructions and inserting processor instructions to set a synchronization bit before a dependence source and to clear the synchronization bit after a dependence source, where the synchronization bit is designed to stall a dependence sink from a thread running on a separate core. Other embodiments are described and claimed.

Abstract translation: 在一个实施例中，本发明引入了一种推测引擎，以通过从串行指令中创建单独的线程并插入处理器指令来在依赖源之前设置同步位并在依赖源之后清除同步位，从而并行化串行指令，其中同步 位被设计为从在单独核心上运行的线程停止依赖宿。 描述和要求保护其他实施例。

公开(公告)号：US07802136B2

公开(公告)日：2010-09-21

申请号：US11648486

申请日：2006-12-28

Applicant: Cheng Wang ,  Youfeng Wu

Inventor： Cheng Wang ,  Youfeng Wu

IPC: G06F11/00

CPC classification number: G06F9/3863 ,  G06F9/3004 ,  G06F9/3834 ,  G06F11/1407

Abstract: A method and apparatus for efficient register checkpointing is herein described. A transaction is detected in program code. A recovery block is inserted in the program code to perform recovery operations in response to an abort of the first transaction. A roll-back edge is potentially inserted from an abort point to the recovery block. A control flow edge is inserted from the recovery block to a entry point of the transaction. Checkpoint code is inserted before the entry point to backup live-in registers in backup storage elements and recovery code is inserted in the recovery block to restore the live-in registers from the backup storage elements in response to an abort of the transaction.

Abstract translation: 这里描述用于有效的寄存器检查点的方法和装置。 在程序代码中检测到事务。 在程序代码中插入恢复块，以响应于第一个事务的中止来执行恢复操作。 回退边缘可能从中止点插入到恢复块。 将控制流程边缘从恢复块插入到事务的入口点。 检查点代码被插入到备份存储元件中的备份实时寄存器的入口点之前，并且恢复代码被插入到恢复块中，以便响应于事务的中止从备份存储元件恢复实时寄存器。

公开(公告)号：US07620781B2

公开(公告)日：2009-11-17

申请号：US11642314

申请日：2006-12-19

Applicant: Mauricio Breternitz, Jr. ,  Youfeng Wu ,  Peter G. Sassone ,  Jeffrey P. Rupley, II ,  Wesley Attrot ,  Bryan Black

Inventor： Mauricio Breternitz, Jr. ,  Youfeng Wu ,  Peter G. Sassone ,  Jeffrey P. Rupley, II ,  Wesley Attrot ,  Bryan Black

IPC: G06F12/0026

CPC classification number: G06F12/0864 ,  Y10S707/99943

Abstract: Implementation of a Bloom filter using multiple single-ported memory slices. A control value is combined with a hashed address value such that the resultant address value has the property that one, and only one, of the k memories or slices is selected for a given input value, a, for each bank. Collisions are thereby avoided and the multiple hash accesses for a given input value, a, may be performed concurrently. Other embodiments are also described and claimed.

Abstract translation: 使用多个单端口存储器片的Bloom过滤器的实现。 控制值与散列地址值组合，使得所得到的地址值具有对于每个存储体的给定输入值a选择k个存储器或片中仅一个且仅一个的属性。 因此避免了冲突，并且可以同时执行给定输入值a的多个哈希访问。 还描述和要求保护其他实施例。

公开(公告)号：US20090172644A1

公开(公告)日：2009-07-02

申请号：US11965271

申请日：2007-12-27

Applicant: Vijayanand Nagarajan ,  Ho-Seop Kim ,  Youfeng Wu ,  Rajiv Gupta

Inventor： Vijayanand Nagarajan ,  Ho-Seop Kim ,  Youfeng Wu ,  Rajiv Gupta

IPC: G06F9/44

CPC classification number: G06F21/566 ,  G06F8/33 ,  G06F11/3636

Abstract: Methods, systems and machine readable media are disclosed for performing dynamic information flow tracking. One method includes executing operations of a program with a main thread, and tracking the main thread's execution of the operations of the program with a tracking thread. The method further includes updating, with the tracking thread, a taint value associated with the value of the main thread to reflect whether the value is tainted, and determining, with the tracking thread based upon the taint value, whether use of the value by the main thread violates a specific security policy.

Abstract translation: 公开了用于执行动态信息流跟踪的方法，系统和机器可读介质。 一种方法包括执行具有主线程的程序的操作，并且使用跟踪线程跟踪主线程对程序的操作的执行。 该方法还包括利用跟踪线程来更新与主线程的值相关联的污点值，以反映该值是否被污染，并且基于该着色值确定跟踪线程是否使用该值 主线程违反了特定的安全策略。

公开(公告)号：US07506217B2

公开(公告)日：2009-03-17

申请号：US11325773

申请日：2005-12-30

Applicant: Edson Borin ,  Cheng C. Wang ,  Youfeng Wu

Inventor： Edson Borin ,  Cheng C. Wang ,  Youfeng Wu

IPC: G06F11/00

CPC classification number: G06F11/1004

Abstract: A method and apparatus for software-based control flow checking for soft error detection. In one embodiment, the method includes the instrumentation of one basic block of a target program to update a signature register with a successor basic block signature at an end of the basic block. In addition, the basic block is instrumented to verify that contents of the signature register match a basic block signature at a beginning of the basic block. In one embodiment, an instruction is inserted within the basic block to cause the signature register to store a predetermined value if the contents of the signature register match a basic block signature. In one embodiment, a basic block may be subdivided into a plurality of regions; each region is assigned a signature and instrumented to update the signature register at a beginning of each region. Other embodiments are described and claimed.

Abstract translation: 一种用于软错误检测的基于软件的控制流程检查的方法和装置。 在一个实施例中，该方法包括在基本块的结尾处对目标程序的一个基本块的仪表进行更新具有后继基本块签名的签名寄存器。 另外，基本块被验证以验证签名寄存器的内容是否与基本块开头的基本块签名相匹配。 在一个实施例中，如果签名寄存器的内容与基本块签名匹配，则在基本块内插入指令以使签名寄存器存储预定值。 在一个实施例中，基本块可以被细分为多个区域; 每个区域都被分配一个签名，并在每个区域的开头进行检测以更新签名寄存器。 描述和要求保护其他实施例。

公开(公告)号：US07467377B2

公开(公告)日：2008-12-16

申请号：US10278682

申请日：2002-10-22

Applicant: Youfeng Wu ,  Li-Ling Chen

Inventor： Youfeng Wu ,  Li-Ling Chen

IPC: G06F9/45 ,  G06F12/00

CPC classification number: G06F12/0888 ,  G06F8/4442 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F12/0897

Abstract: Methods and apparatus to manage bypassing of a first cache are disclosed. In one such method, a load instruction having an expected latency greater than or equal to a predetermined threshold is identified. A request is then made to schedule the identified load instruction to have a predetermined latency. The software program is then scheduled. An actual latency associated with the load instruction in the scheduled software program is then compared to the predetermined latency. If the actual latency is greater than or equal to the predetermined latency, the load instruction is marked to bypass the first cache.

Abstract translation: 公开了管理第一高速缓存的旁路的方法和装置。 在一种这样的方法中，识别具有大于或等于预定阈值的预期等待时间的加载指令。 然后进行请求以将所识别的加载指令调度为具有预定的延迟。 然后安排软件程序。 然后将与预定软件程序中的加载指令相关联的实际延迟与预定延迟进行比较。 如果实际延迟大于或等于预定延迟，则加载指令被标记为绕过第一高速缓存。

公开(公告)号：US20080244538A1

公开(公告)日：2008-10-02

申请号：US11728347

申请日：2007-03-26

Applicant: Sreekumar R. Nair ,  Youfeng Wu

Inventor： Sreekumar R. Nair ,  Youfeng Wu

IPC: G06F9/45

CPC classification number: G06F9/45554

Abstract: A processor virtualization abstracts the behavior of a processor instruction set architecture from an underlying micro-architecture implementation. It is capable of running any processor instruction set architecture compatible software on any micro-architecture implementation. A system wide dynamic binary translator translates source system programs to target programs and manages the execution of those target programs. It also provides the necessary and sufficient infrastructure requires to render multi-core processor virtualization.

Abstract translation: 处理器虚拟化从基础微架构实现中抽象出处理器指令集架构的行为。 它能够在任何微架构实现上运行任何处理器指令集架构兼容的软件。 系统的动态二进制翻译器将源系统程序转换为目标程序，并管理这些目标程序的执行。 它还提供了必要和足够的基础架构来呈现多核处理器虚拟化。

公开(公告)号：US20080162990A1

公开(公告)日：2008-07-03

申请号：US11648486

申请日：2006-12-28

Applicant: Cheng Wang ,  Youfeng Wu

Inventor： Cheng Wang ,  Youfeng Wu

IPC: G06F11/07

CPC classification number: G06F9/3863 ,  G06F9/3004 ,  G06F9/3834 ,  G06F11/1407

Abstract: A method and apparatus for efficient register checkpointing is herein described. A transaction is detected in program code. A recovery block is inserted in the program code to perform recovery operations in response to an abort of the first transaction. A roll-back edge is potentially inserted from an abort point to the recovery block. A control flow edge is inserted from the recovery block to a entry point of the transaction. Checkpoint code is inserted before the entry point to backup live-in registers in backup storage elements and recovery code is inserted in the recovery block to restor the live-in registers from the backup storage elements in response to an abort of the transaction.

Abstract translation: 这里描述用于有效的寄存器检查点的方法和装置。 在程序代码中检测到事务。 在程序代码中插入恢复块，以响应于第一个事务的中止来执行恢复操作。 回退边缘可能从中止点插入到恢复块。 将控制流程边缘从恢复块插入到事务的入口点。 检查点代码被插入到备份存储元件中的备份实时寄存器的入口点之前，并且恢复代码被插入到恢复块中以便从备份存储元件恢复实时寄存器以响应中止事务。