公开(公告)号：US20130271452A1

公开(公告)日：2013-10-17

申请号：US13977657

申请日：2011-09-30

Applicant: Arvind Kumar ,  Mark D. Yarvis ,  Christopher J. Lord

Inventor： Arvind Kumar ,  Mark D. Yarvis ,  Christopher J. Lord

IPC: G06T17/00

CPC classification number: G06F3/14 ,  G06F3/04815 ,  G06T17/00 ,  G09G5/00 ,  G09G2320/0693 ,  G09G2340/02 ,  G09G2354/00 ,  G09G2360/121

Abstract: A mechanism is described for facilitating context-aware composition and rendering of virtual models and/or images of physical objects computationally composited and rendered at computing devices according to one embodiment of the invention. A method of embodiments of the invention includes performing initial calibration of a plurality of computing devices to provide point of view positions of a scene according to a location of each of the plurality of computing devices with respect to the scene, where computing devices of the plurality of computing devices are in communication with each other over a network. The method may further include generating context-aware views of the scene based on the point of view positions of the plurality of computing devices, where each context-aware view corresponds to a computing device. The method may further include generating images of the scene based on the context-aware views of the scene, where each image corresponds to a computing device, and displaying each image at its corresponding computing device.

Abstract translation: 描述了一种机制，用于促进根据本发明的一个实施例的在计算设备处计算地合成和呈现的物理对象的虚拟模型和/或图像的上下文感知组合和呈现。 本发明的实施例的方法包括执行多个计算设备的初始校准，以根据多个计算设备中的每一个相对于场景的位置来提供场景的位置，其中多个计算设备的计算设备 的计算设备通过网络彼此通信。 该方法还可以包括基于多个计算设备的观点位置来生成场景的上下文感知视图，其中每个上下文感知视图对应于计算设备。 该方法还可以包括基于场景的上下文感知视图来生成场景的图像，其中每个图像对应于计算设备，并且在其相应的计算设备处显示每个图像。

公开(公告)号：US08510569B2

公开(公告)日：2013-08-13

申请号：US12639616

申请日：2009-12-16

Applicant: Ned Smith ,  Vedvyas Shanbhogue ,  Arvind Kumar ,  Purushottam Goel

Inventor： Ned Smith ,  Vedvyas Shanbhogue ,  Arvind Kumar ,  Purushottam Goel

IPC: G06F9/30 ,  G06F21/22

CPC classification number: G06F21/554 ,  G06F21/44 ,  G06F21/57 ,  G06F21/64

Abstract: In one embodiment, a processor includes a microcode storage including processor instructions to create and execute a hidden resource manager (HRM) to execute in a hidden environment that is not visible to system software. The processor may further include an extend register to store security information including a measurement of at least one kernel code module of the hidden environment and a status of a verification of the at least one kernel code module. Other embodiments are described and claimed.

公开(公告)号：US08299519B2

公开(公告)日：2012-10-30

申请号：US12685335

申请日：2010-01-11

Applicant: Anthony I. Chou ,  Arvind Kumar

Inventor： Anthony I. Chou ,  Arvind Kumar

IPC: H01L27/092

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/11558 ,  H01L29/1087 ,  H01L29/78615

Abstract: A read transistor for single poly non-volatile memory using a body contacted SOI transistor and a method of manufacturing the same is provided. The non-volatile random access memory is formed in silicon on insulator (SOI). The non-volatile random access memory includes a read field effect transistor (FET) having a body contact formed in the silicon of the SOI. The body contact is in electrical contact with a diffusion region under a gate of the read FET.

Abstract translation: 提供了一种用于使用身体接触的SOI晶体管的单个多重非易失性存储器的读取晶体管及其制造方法。 非易失性随机存取存储器形成在绝缘体上硅（SOI）中。 非易失性随机存取存储器包括在SOI的硅中形成有体接触的读取场效应晶体管（FET）。 身体接触与读取FET的栅极下方的扩散区域电接触。

公开(公告)号：US20120217585A1

公开(公告)日：2012-08-30

申请号：US13468270

申请日：2012-05-10

Applicant: Hasan M. Nayfeh ,  Andres Bryant ,  Arvind Kumar ,  Nivo Rovedo ,  Robert R. Robison

Inventor： Hasan M. Nayfeh ,  Andres Bryant ,  Arvind Kumar ,  Nivo Rovedo ,  Robert R. Robison

IPC: H01L27/088

CPC classification number: H01L21/26586 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66659

Abstract: A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.

Abstract translation: 在基板上形成多个栅极结构。 每个栅极结构包括第一栅极电极和源极和漏极区域。 从每个栅极结构去除第一栅电极。 施加第一光致抗蚀剂以在源向下方向上阻挡具有源极区的栅极结构。 在栅极结构中进行第一光晕注入，其栅源结构的源极区域在源极方向上以第一角度。 去除第一光致抗蚀剂。 施加第二光致抗蚀剂以阻挡在源向上方向上具有源极区的栅极结构。 在栅极结构中进行第二光晕注入，其栅源结构的源极区域以源向下方向为第二角度。 去除第二光致抗蚀剂。 在每个栅极结构中形成替代栅电极。

公开(公告)号：US08232151B2

公开(公告)日：2012-07-31

申请号：US13167303

申请日：2011-06-23

Applicant: Hasan M. Nayfeh ,  Andres Bryant ,  Arvind Kumar ,  Nivo Rovedo ,  Robert R. Robison

Inventor： Hasan M. Nayfeh ,  Andres Bryant ,  Arvind Kumar ,  Nivo Rovedo ,  Robert R. Robison

IPC: H01L21/336

CPC classification number: H01L21/26586 ,  H01L29/1083 ,  H01L29/66492 ,  H01L29/66545 ,  H01L29/66659

Abstract: A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.

Abstract translation: 在基板上形成多个栅极结构。 每个栅极结构包括第一栅极电极和源极和漏极区域。 从每个栅极结构去除第一栅电极。 施加第一光致抗蚀剂以在源向下方向上阻挡具有源极区的栅极结构。 在栅极结构中进行第一光晕注入，其栅源结构的源极区域在源极方向上以第一角度。 去除第一光致抗蚀剂。 施加第二光致抗蚀剂以阻挡在源向上方向上具有源极区的栅极结构。 在栅极结构中进行第二光晕注入，其栅源结构的源极区域以源向下方向为第二角度。 去除第二光致抗蚀剂。 在每个栅极结构中形成替代栅电极。

公开(公告)号：US08212322B2

公开(公告)日：2012-07-03

申请号：US12720354

申请日：2010-03-09

Applicant: Martin M. Frank ,  Arvind Kumar ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Jeffrey Sleight

Inventor： Martin M. Frank ,  Arvind Kumar ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Jeffrey Sleight

IPC: H01L21/8234 ,  H01L21/8244

CPC classification number: H01L27/1104 ,  H01L27/11 ,  H01L27/1108

Abstract: Techniques for combining transistors having different threshold voltage requirements from one another are provided. In one aspect, a semiconductor device comprises a substrate having a first and a second nFET region, and a first and a second pFET region; a logic nFET on the substrate over the first nFET region; a logic pFET on the substrate over the first pFET region; a SRAM nFET on the substrate over the second nFET region; and a SRAM pFET on the substrate over the second pFET region, each comprising a gate stack having a metal layer over a high-K layer. The logic nFET gate stack further comprises a capping layer separating the metal layer from the high-K layer, wherein the capping layer is further configured to shift a threshold voltage of the logic nFET relative to a threshold voltage of one or more of the logic pFET, SRAM nFET and SRAM pFET.

Abstract translation: 提供了用于组合彼此具有不同阈值电压要求的晶体管的技术。 在一个方面，一种半导体器件包括具有第一和第二nFET区的衬底以及第一和第二pFET区; 在第一nFET区域上的衬底上的逻辑nFET; 在第一pFET区上的衬底上的逻辑pFET; 位于第二nFET区上的衬底上的SRAM nFET; 以及在第二pFET区上的衬底上的SRAM pFET，每个包括在高K层上具有金属层的栅极堆叠。 逻辑nFET栅极堆叠还包括将金属层与高K层分隔开的覆盖层，其中封盖层还被配置为相对于逻辑pFET中的一个或多个的阈值电压移动逻辑nFET的阈值电压 ，SRAM nFET和SRAM pFET。

公开(公告)号：US08030145B2

公开(公告)日：2011-10-04

申请号：US12684225

申请日：2010-01-08

Applicant: Leland Chang ,  Brian L. Ji ,  Arvind Kumar ,  Amlan Majumdar ,  Katherine Saenger ,  Leathen Shi ,  Jeng-Bang Yau

Inventor： Leland Chang ,  Brian L. Ji ,  Arvind Kumar ,  Amlan Majumdar ,  Katherine Saenger ,  Leathen Shi ,  Jeng-Bang Yau

IPC: H01L21/84

CPC classification number: H01L21/2652 ,  G03F9/7084 ,  H01L21/26506 ,  H01L21/2654 ,  H01L21/26553 ,  H01L21/2658 ,  H01L21/6835 ,  H01L23/544 ,  H01L29/78648 ,  H01L2221/68318 ,  H01L2221/68363 ,  H01L2221/68377 ,  H01L2223/54426 ,  H01L2224/80006 ,  H01L2224/8013 ,  H01L2224/802 ,  H01L2924/01019 ,  H01L2924/12044 ,  H01L2924/13091

Abstract: A fully depleted semiconductor-on-insulator (FDSOI) transistor structure includes a back gate electrode having a limited thickness and aligned to a front gate electrode. The back gate electrode is formed in a first substrate by ion implantation of dopants through a first oxide cap layer. Global alignment markers are formed in the first substrate to enable alignment of the front gate electrode to the back gate electrode. The global alignment markers enable preparation of a virtually flat substrate on the first substrate so that the first substrate can be bonded to a second substrate in a reliable manner.

Abstract translation: 完全耗尽的绝缘体上半导体（FDSOI）晶体管结构包括具有有限厚度并与前栅电极对准的背栅电极。 背栅极通过第一氧化物覆盖层通过离子注入掺杂剂形成在第一衬底中。 在第一衬底中形成全局对准标记，以使前栅电极与背栅电极对准。 全局校准标记使得能够在第一衬底上制备实质上平坦的衬底，使得第一衬底可以以可靠的方式结合到第二衬底。

公开(公告)号：US20110169064A1

公开(公告)日：2011-07-14

申请号：US12685335

申请日：2010-01-11

Applicant: Anthony I. Chou ,  Arvind Kumar

Inventor： Anthony I. Chou ,  Arvind Kumar

IPC: H01L29/94 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/11558 ,  H01L29/1087 ,  H01L29/78615

Abstract: A read transistor for single poly non-volatile memory using a body contacted SOI transistor and a method of manufacturing the same is provided. The non-volatile random access memory is formed in silicon on insulator (SOI). The non-volatile random access memory includes a read field effect transistor (FET) having a body contact formed in the silicon of the SOI. The body contact is in electrical contact with a diffusion region under a gate of the read FET.

Abstract translation: 提供了一种用于使用身体接触的SOI晶体管的单个多重非易失性存储器的读取晶体管及其制造方法。 非易失性随机存取存储器形成在绝缘体上硅（SOI）中。 非易失性随机存取存储器包括在SOI的硅中形成有体接触的读取场效应晶体管（FET）。 身体接触与读取FET的栅极下方的扩散区域电接触。

公开(公告)号：US20110145274A1

公开(公告)日：2011-06-16

申请号：US12639648

申请日：2009-12-16

Applicant: Gopal Avinash ,  Chetan Hd ,  Arun Kumar Chandrashekarappa ,  Arvind Kumar ,  Raja Shekhara

Inventor： Gopal Avinash ,  Chetan Hd ,  Arun Kumar Chandrashekarappa ,  Arvind Kumar ,  Raja Shekhara

IPC: G06F17/30 ,  G06F3/048

CPC classification number: G06F19/321

Abstract: Systems, methods and mediums with instructions for viewing medical data are provided. A system for viewing medical data can include a computer processor, a database and a user interface. The database can include numerous entries from numerous clinical modalities. Each entry can include image data and/or non-image data. Each entry can include annotated medical information from a previous study. The annotated medical information can include comments and markings. The database can be searchable to identify an entry based on input medical information relating to a current study. The user interface can be configured to simultaneously display annotated medical information from an identified entry and medical information from the current study. The system can further include a second user interface configured to display medical information, allow a user to annotate the medical information, and allow the user to save the annotated medical information as an entry in the database.

Abstract translation: 提供了具有查看医疗数据说明的系统，方法和介质。 用于查看医疗数据的系统可以包括计算机处理器，数据库和用户界面。 数据库可以包括许多临床模式的许多条目。 每个条目可以包括图像数据和/或非图像数据。 每个条目都可以包括以前研究的注释医学信息。 注释的医疗信息可以包括评论和标记。 可以搜索数据库以基于与当前研究相关的输入医疗信息来识别条目。 用户界面可以被配置为从当前研究中同时显示来自识别的条目的注释医学信息和医学信息。 该系统还可以包括被配置为显示医疗信息的第二用户界面，允许用户注释医疗信息，并允许用户将注释的医疗信息作为条目存储在数据库中。

公开(公告)号：US07956415B2

公开(公告)日：2011-06-07

申请号：US12133686

申请日：2008-06-05

Applicant: Anthony I. Chou ,  Andres Bryant ,  Arvind Kumar ,  Shreesh Narasimha

Inventor： Anthony I. Chou ,  Andres Bryant ,  Arvind Kumar ,  Shreesh Narasimha

IPC: H01L27/12

CPC classification number: H01L29/66772 ,  H01L29/78603 ,  H01L29/78612

Abstract: A top semiconductor layer is formed with two different thicknesses such that a step is formed underneath a body region of a semiconductor-on-insulator (SOI) field effect transistor at the interface between a top semiconductor layer and an underlying buried insulator layer. The interface and the accompanying interfacial defects in the body region provide recombination centers, which increase the recombination rate between the holes and electrons in the body region. Optionally, a spacer portion, comprising a material that functions as recombination centers, is formed on sidewalls of the step to provide an enhanced recombination rate between holes and electrons in the body region, which increases the bipolar breakdown voltage of a SOI field effect transistor.

Abstract translation: 顶部半导体层形成有两个不同的厚度，使得在顶部半导体层和下面的掩埋绝缘体层之间的界面处在绝缘体上半导体（SOI）场效应晶体管的体区之下形成台阶。 身体区域中的界面和伴随的界面缺陷提供了复合中心，这增加了身体区域中的空穴和电子之间的复合速率。 任选地，包括作为复合中心的材料的间隔物部分形成在台阶的侧壁上，以在体区中的空穴和电子之间提供增强的复合率，这增加了SOI场效应晶体管的双极击穿电压。