Adjustable write pulse generator within a chalcogenide memory device
    91.
    发明授权
    Adjustable write pulse generator within a chalcogenide memory device 有权
    可变写脉冲发生器在硫族化物存储器件内

    公开(公告)号:US08059454B2

    公开(公告)日:2011-11-15

    申请号:US12531851

    申请日:2008-12-01

    IPC分类号: G11C7/00

    摘要: An adjustable write pulse generator is disclosed. The adjustable write pulse generator includes a band-gap reference current, a programmable ring oscillator, a frequency divider and a single pulse generator. The band-gap reference current circuit generates a well-compensated current over a predetermined range of temperatures needed to program a chalcogenide memory cell. The programmable ring oscillator generates a first set of continuous write “0” and write “1” pulse signals based on the well-compensated current. The frequency divider then divides the first set of continuous write “0” and write “1” pulse signals into a second set of continuous write “0” and write “1” pulse signals. The single pulse generator subsequently converts the second set of continuous write “0” and write “1” pulse signals into a single write “0” pulse signal or a single write “1” pulse signal when programming the chalcogenide memory cell.

    摘要翻译: 公开了一种可调写入脉冲发生器。 可调写脉冲发生器包括带隙参考电流,可编程环形振荡器,分频器和单脉冲发生器。 带隙参考电流电路在编程硫属化物存储器单元所需的温度的预定范围内产生良好补偿的电流。 可编程环形振荡器基于良好补偿的电流产生第一组连续写入“0”和写入“1”脉冲信号。 分频器然后将第一组连续写入“0”和“1”脉冲信号分成第二组连续写“0”和写“1”脉冲信号。 当编程硫族化物存储单元时,单脉冲发生器随后将第二组连续写入“0”和“1”脉冲信号转换为单个写入“0”脉冲信号或单个写入“1”脉冲信号。

    Non-volatile single-event upset tolerant latch circuit
    93.
    发明授权
    Non-volatile single-event upset tolerant latch circuit 有权
    非易失性单事件容错锁存电路

    公开(公告)号:US07965541B2

    公开(公告)日:2011-06-21

    申请号:US12525458

    申请日:2008-11-25

    IPC分类号: G11C11/00

    摘要: A non-volatile single-event upset (SEU) tolerant latch is disclosed. The non-volatile SEU tolerant latch includes a first and second inverters connected to each other in a cross-coupled manner. The gates of transistors within the first inverter are connected to the drains of transistors within the second inverter via a first feedback resistor. Similarly, the gates of transistors within the second inverter are connected to the drains of transistors within the first inverter via a second feedback resistor. The non-volatile SEU tolerant latch also includes a pair of chalcogenide memory elements connected to the inverters for storing information.

    摘要翻译: 公开了一种非易失性单事件镦粗(SEU)容错锁存器。 非易失性SEU容限锁存器包括以交叉耦合方式彼此连接的第一和第二反相器。 第一反相器内的晶体管的栅极通过第一反馈电阻连接到第二反相器内的晶体管的漏极。 类似地,第二反相器内的晶体管的栅极经由第二反馈电阻器连接到第一反相器内的晶体管的漏极。 非易失性SEU容限锁存器还包括连接到逆变器的一对硫族化物存储元件,用于存储信息。

    Pen
    94.
    外观设计
    Pen 有权

    公开(公告)号:USD628634S1

    公开(公告)日:2010-12-07

    申请号:US29353761

    申请日:2010-01-13

    申请人: Bin Li

    设计人: Bin Li

    HARDENED CURRENT MODE LOGIC (CML) VOTER CIRCUIT, SYSTEM AND METHOD
    95.
    发明申请
    HARDENED CURRENT MODE LOGIC (CML) VOTER CIRCUIT, SYSTEM AND METHOD 有权
    硬化电流模式逻辑(CML)VOTER CIRCUIT,SYSTEM AND METHOD

    公开(公告)号:US20100141296A1

    公开(公告)日:2010-06-10

    申请号:US12595865

    申请日:2008-12-10

    IPC分类号: H03K19/003 H03K19/094

    CPC分类号: H03K19/23

    摘要: A current mode logic voter circuit includes three two-input split NOR gates. Each two-input split NOR gate receives a corresponding pair of input signals and generates a pair of first output signals responsive to the input signals. A three input split NOR gate is coupled to the two-input split NOR gates to receive the first output signals and generates a second pair of output signals responsive to the first output signals from the two-input split NOR gates. The two and three-input split NOR gates can be formed from current mode logic buffer circuits, and in one embodiment in the three-input split NOR gate the buffer circuits are hardened.

    摘要翻译: 电流模式逻辑选择电路包括三个双输入分频NOR门。 每个双输入分频NOR门接收相应的输入信号对,并根据输入信号产生一对第一输出信号。 三输入分频NOR门耦合到双输入分频NOR门以接收第一输出信号,并响应于来自双输入分频NOR门的第一输出信号产生第二对输出信号。 两个和三个输入的分频NOR门可以由电流模式逻辑缓冲电路形成,并且在一个实施例中,在三输入分频NOR门中,缓冲电路被硬化。

    Steganalysis of Suspect Media
    96.
    发明申请
    Steganalysis of Suspect Media 有权
    可疑媒体的分析

    公开(公告)号:US20100091981A1

    公开(公告)日:2010-04-15

    申请号:US12422677

    申请日:2009-04-13

    申请人: Yun-Qing Shi Bin Li

    发明人: Yun-Qing Shi Bin Li

    IPC分类号: H04K1/00 G06K9/00

    摘要: Techniques described herein are generally related to steganalysis of suspect media. Steganalysis techniques may include receiving instances of suspect media as input for steganalytic processing. A first set of quantized blocks of data elements may be identified within the media, with this first set of blocks being eligible to be embedded with steganographic data. A second set of quantized blocks of data elements may be identified within the media, with this second set of blocks being ineligible to be embedded with steganographic data. The steganalysis techniques may requantize the first and second blocks. In turn, these techniques may compare statistics resulting from requantizing the first block with statistics resulting from requantizing the second block. The steganalysis techniques may then assess whether the first block of data elements is embedded with steganographic features based on how the statistics of the second blocks compare with the statistics of the first blocks.

    摘要翻译: 本文描述的技术通常涉及可疑介质的隐写分析。 隐匿分析技术可以包括接收可疑媒体的实例作为隐写处理的输入。 可以在媒体内识别数据元素的第一组量化块,其中该第一组块有资格嵌入隐写数据。 可以在媒体内识别第二组数据元素的量化块,其中第二组块不符合隐写数据​​的嵌入。 隐写分析技术可以重新调整第一和第二块。 反过来,这些技术可以将从重新量化第一个块得到的统计数据与由再量化第二个块产生的统计数据进行比较。 隐写分析技术可以基于第二块的统计数据如何与第一块的统计量进行比较来评估第一块数据元素是否嵌入隐写特征。

    Analog Access Circuit for Validating Chalcogenide Memory Cells
    97.
    发明申请
    Analog Access Circuit for Validating Chalcogenide Memory Cells 有权
    用于验证硫族化物记忆体的模拟电路

    公开(公告)号:US20100074000A1

    公开(公告)日:2010-03-25

    申请号:US12525510

    申请日:2008-11-26

    IPC分类号: G11C7/00 G11C11/00

    摘要: An analog access circuit for characterizing chalcogenide memory cells is disclosed. The analog access circuit includes an analog access control module, an address and data control module, and an analog cell access and current monitoring module. The analog access control module selectively controls whether a normal memory access or an analog memory access should be performed on a specific chalcogenide memory cell. The address and data control module allows a normal memory access to the chalcogenide memory cell according to an input address. The analog cell access and current monitoring module performs an analog memory access to the chalcogenide memory cell according to the input address, and monitors a reference current from a sense amplifier associated with the chalcogenide memory cell.

    摘要翻译: 公开了一种用于表征硫族化物存储器单元的模拟存取电路。 模拟访问电路包括模拟访问控制模块,地址和数据控制模块以及模拟单元访问和电流监控模块。 模拟访问控制模块选择性地控制是否应该在特定的硫族化物存储器单元上执行正常存储器存取或模拟存储器访问。 地址和数据控制模块允许根据输入地址对硫属化物存储器单元进行正常存储器访问。 模拟电池接入和电流监测模块根据输入地址对硫族化物存储单元进行模拟存储器存取,并监测来自与硫族化物存储单元相关联的读出放大器的参考电流。

    COMPOSITIONS AND METHODS FOR MODULATION OF SUPPRESSOR T CELL ACTIVATION
    98.
    发明申请
    COMPOSITIONS AND METHODS FOR MODULATION OF SUPPRESSOR T CELL ACTIVATION 审中-公开
    用于调节抑制剂T细胞活化的组合物和方法

    公开(公告)号:US20100061984A1

    公开(公告)日:2010-03-11

    申请号:US12161192

    申请日:2007-01-22

    摘要: Methods of treating autoimmune disorders, coronary artery disease, allergy symptoms, allograft rejection sepsis/toxic shock are disclosed. Some methods comprise administering one or more regulatory compositions to activate the T suppressor cells by increasing the acetylation level and/or protein level of FOXP3 in combination with a T suppressor stimulus and/or an antigen. Some methods comprise administering one or more regulatory compositions to activate the T suppressor cells by increasing the acetylation level and/or protein level of FOXP3. Some methods comprise administering soluble GITR or antibodies that bind to GITR ligand. Methods of treating cancer, infectious diseases, and immune deficiency are also disclosed as are vaccination methods. The methods comprise administering one or more regulatory compositions to inactivate the T suppressor cells by reducing the acetylation level and/or protein level of FOXP3. Improved vaccines and vaccination methods are disclosed. Methods of identifying compounds that are useful to modulate acetylation level and/or protein level of FOXP3 and treat diseases are disclosed.

    摘要翻译: 公开了治疗自身免疫性疾病,冠状动脉疾病,过敏症状,同种异体移植排斥败血症/中毒性休克的方法。 一些方法包括施用一种或多种调节组合物以通过与T抑制刺激和/或抗原组合增加FOXP3的乙酰化水平和/或蛋白水平来激活T抑制细胞。 一些方法包括施用一种或多种调节组合物以通过增加FOXP3的乙酰化水平和/或蛋白水平来激活T抑制细胞。 一些方法包括施用可结合GITR配体的可溶性GITR或抗体。 疫苗接种方法也公开了治疗癌症,感染性疾病和免疫缺陷的方法。 所述方法包括施用一种或多种调节组合物以通过降低FOXP3的乙酰化水平和/或蛋白质水平来灭活T抑制细胞。 公开了改进的疫苗和疫苗接种方法。 公开了鉴定可用于调节FOXP3的乙酰化水平和/或蛋白质水平并治疗疾病的化合物的方法。

    DITHIOLOPYRROLONES COMPOUNDS AND THEIR THERAPEUTIC APPLICATIONS
    99.
    发明申请
    DITHIOLOPYRROLONES COMPOUNDS AND THEIR THERAPEUTIC APPLICATIONS 有权
    二羟基吡咯烷酮化合物及其治疗应用

    公开(公告)号:US20100041729A1

    公开(公告)日:2010-02-18

    申请号:US12440331

    申请日:2007-09-10

    IPC分类号: A61K31/407 C07D495/04

    CPC分类号: C07D495/04

    摘要: The present invention provides dithiolopyrrolone compounds of the general formula I, and their salts, wherein A is sulfur or carbon, and R1, R2, and R3 are selected from groups defined herein, and wherein when A is sulfur, then B is oxygen, and n=1 or 2, and when A is carbon, then B is oxygen or sulfur, and n=1. The compounds are useful for the prevention and treatment of microbial infections such as HIV infection, and for the treatment of blood disorders, such as neutropenia. In particular, the compounds are useful for the manufacture of medicaments for increasing white blood cells.

    摘要翻译: 本发明提供通式I的二硫代环吡咯酮化合物及其盐,其中A为硫或碳,R1,R2和R3选自本文定义的基团,其中当A为硫时,B为氧, n = 1或2,当A为碳时,B为氧或硫,n = 1。 这些化合物可用于预防和治疗诸如HIV感染的微生物感染,以及用于治疗血液病症,例如中性白细胞减少症。 特别地,这些化合物可用于制备用于增加白细胞的药物。

    System for ensuring quality of service in a virtual private network and method thereof
    100.
    发明授权
    System for ensuring quality of service in a virtual private network and method thereof 有权
    用于确保虚拟专用网络中的服务质量的系统及其方法

    公开(公告)号:US07650637B2

    公开(公告)日:2010-01-19

    申请号:US10586604

    申请日:2005-01-12

    IPC分类号: H04L29/00

    摘要: A system for ensuring quality of service (QoS) in a virtual private network and a method thereof are provided. The system includes a logical bearer network, which is formed by connecting label switch paths configured with preserving bandwidth to routers, and is dedicated to transmit QoS service data; and a bearer control network, which is used to maintain logical bearer network, allocate route, mark service priority, and route service data to opposite end. The method includes the steps of: A. constructing a logical bearer network to transmit QoS service data by configuring label switch paths with preserved bandwidth; B. providing a centralized resource controller to manage resources of the logical bearer network; C. if QoS service data is to be transmitted, marking service priority in QoS field of the routing labels of multi-protocol label switch data packets, and routing service data to the opposite end.

    摘要翻译: 提供了一种用于确保虚拟专用网络中的服务质量(QoS)的系统及其方法。 该系统包括通过将配置有保留带宽的标签交换路径连接到路由器而形成的逻辑承载网,专用于传输QoS服务数据; 以及承载控制网络,用于维护逻辑承载网,分配路由,标记业务优先级,并将业务数据路由到对端。 该方法包括以下步骤:A.通过配置带有保留带宽的标签交换路径,构建逻辑承载网,传输QoS业务数据; B.提供集中资源控制器来管理逻辑承载网的资源; C.如果要发送QoS服务数据,则在多协议标签交换机数据包的路由标签的QoS字段中标记服务优先级,并将路由服务数据转发到对端。