公开(公告)号：US07480772B2

公开(公告)日：2009-01-20

申请号：US11835984

申请日：2007-08-08

申请人： James Stephen Fields, Jr. ,  Benjiman Lee Goodman ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams

发明人： James Stephen Fields, Jr. ,  Benjiman Lee Goodman ,  Guy Lynn Guthrie ,  William John Starke ,  Derek Edward Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0817 ,  G06F12/0831 ,  G06F12/084

摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache memory. The first cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the memory block is possibly shared with the second cache memory in the first coherency domain and cached only within the first coherency domain.

摘要翻译： 高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元。 第一相关域包括第一高速缓存存储器和第二高速缓冲存储器，并且第二相干域包括远程一致高速缓存存储器。 第一高速缓存存储器包括高速缓存控制器，包括用于高速缓存存储器块的数据存储位置的数据阵列和高速缓存目录。 缓存目录包括用于存储与存储器块相关联的地址标签的标签字段和与标签字段和数据存储位置相关联的一致性状态字段。 相关性状态字段具有多个可能的状态，包括指示存储器块可能与第一相关域中的第二高速缓冲存储器共享并且仅在第一相干域内缓存的状态。

公开(公告)号：US20080140953A1

公开(公告)日：2008-06-12

申请号：US12033454

申请日：2008-02-19

申请人： Guy Lynn Guthrie ,  Hugh Shen ,  Derek Edward Williams

发明人： Guy Lynn Guthrie ,  Hugh Shen ,  Derek Edward Williams

IPC分类号： G06F12/00

CPC分类号： G06F9/30087 ,  G06F9/3004 ,  G06F9/3824 ,  G06F9/3834 ,  G06F9/3851

摘要： A method, system, and processor chip design for reducing the latency between completing a LARX operation and receiving the associated STCX operation to complete the update to the cache line. Each entry of the store queue of the issuing processor is provided an additional tracking bit (priority bit). The priority bit is set whenever a STCX operation is placed within the entry. During selection of an entry for dispatch by the arbitration logic, the arbitration logic scans the value of the priority bits of each eligible entry. An entry with the priority bit set is given priority in the selection process within architectural rules. That entry is then selected for dispatch as early as is possible within the established rules.

公开(公告)号：US07356568B2

公开(公告)日：2008-04-08

申请号：US10318514

申请日：2002-12-12

申请人： Ravi Kumar Arimilli ,  Robert Alan Cargnoni ,  Derek Edward Williams ,  Kenneth Lee Wright

发明人： Ravi Kumar Arimilli ,  Robert Alan Cargnoni ,  Derek Edward Williams ,  Kenneth Lee Wright

IPC分类号： G06F13/00

CPC分类号： G06F9/30101

摘要： A processor communication register (PCR) contained in each processor within a multiprocessor system provides enhanced processor communication. Each PCR stores identical processor communication information that is useful in pipelined or parallel multi-processing. Each processor has exclusive rights to store to a sector within each PCR and has continuous access to read the contents of its own PCR. Each processor updates its exclusive sector within all of the PCRs, instantly allowing all of the other processors to see the change within the PCR data, and bypassing the cache subsystem. Efficiency is enhanced within the multiprocessor system by providing processor communications to be immediately transferred into all processors without momentarily restricting access to the information or forcing all the processors to be continually contending for the same cache line, and thereby overwhelming the interconnect and memory system with an endless stream of load, store and invalidate commands.

摘要翻译： 包含在多处理器系统内的每个处理器中的处理器通信寄存器（PCR）提供增强的处理器通信。 每个PCR存储在流水线或并行多处理中有用的相同的处理器通信信息。 每个处理器具有存储在每个PCR内的扇区的专有权利，并且具有连续访问以读取其自己的PCR的内容。 每个处理器在所有PCR中更新其独占扇区，立即允许所有其他处理器查看PCR数据中的更改，并绕过缓存子系统。 通过提供处理器通信以立即转移到所有处理器中而不会立即限制对信息的访问或迫使所有处理器连续地竞争相同的高速缓存行，从而将互连和存储系统压倒在一起，从而在多处理器系统中提高效率 无限流的加载，存储和无效命令。

公开(公告)号：US07197604B2

公开(公告)日：2007-03-27

申请号：US10965151

申请日：2004-10-14

申请人： Guy Lynn Guthrie ,  Sheldon B. Levenstein ,  William John Starke ,  Derek Edward Williams

发明人： Guy Lynn Guthrie ,  Sheldon B. Levenstein ,  William John Starke ,  Derek Edward Williams

IPC分类号： G06F12/00

CPC分类号： G06F12/0875 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3851

摘要： A processing unit for a multiprocessor data processing system includes a processor core including a store-through upper level cache, an instruction sequencing unit that fetches instructions for execution, a data register, and at least one instruction execution unit. The instruction execution unit, responsive to receipt of a load-reserve instruction from the instruction sequencing unit, executes the load-reserve instruction to determine a load target address. The processor core, responsive to the execution of the load-reserve instruction, performs a corresponding load-reserve operation by accessing the store-through upper level cache utilizing the load target address to cause data associated with the load target address to be loaded from the store-through upper level cache into the data register and by establishing a reservation for a reservation granule including the load target address.

摘要翻译： 一种用于多处理器数据处理系统的处理单元，包括：处理器核心，包括存储器上级缓存器，指令执行指令排序单元，数据寄存器和至少一个指令执行单元。 指令执行单元响应于从指令排序单元接收到加载保留指令，执行加载保留指令以确定加载目标地址。 处理器核心响应于负载预留指令的执行，通过使用负载目标地址访问存储上级高速缓存来执行相应的加载备份操作，以使与加载目标地址相关联的数据从 通过上层缓存到数据寄存器中，并通过建立包括加载目标地址的预留颗粒的预留。

公开(公告)号：US07017031B2

公开(公告)日：2006-03-21

申请号：US10268740

申请日：2002-10-10

申请人： Ravi Kumar Arimilli ,  Derek Edward Williams

发明人： Ravi Kumar Arimilli ,  Derek Edward Williams

IPC分类号： G06F9/30

CPC分类号： G06F12/0815 ,  G06F9/3004 ,  G06F9/30072 ,  G06F9/30087 ,  G06F12/0811

摘要： A data processing system includes a global promotion facility containing a plurality of promotion bit fields, an interconnect, and a plurality of processing units coupled to the global promotion facility and to the interconnect. A first processing unit includes an instruction sequencing unit, an execution unit that executes an acquisition instruction to acquire a particular promotion bit field within the global promotion facility, and a promotion awareness facility. In response to the first processing unit snooping a request by a second processing unit for the particular promotion bit field, the first processing unit records an association between the second processing unit and the particular promotion bit field in the global promotion facility. After the request and release of the particular promotion bit field by the first processing unit, the first processing unit checks the promotion awareness facility for an association for the particular promotion bit and responsive to the checking, pushes the particular promotion bit field to the second processing unit utilizing an unsolicited operation on the interconnect such that no additional request by the second processing unit is required.

摘要翻译： 数据处理系统包括包含多个升级位字段的全球推广设施，互连以及耦合到全球促销设施和互连的多个处理单元。 第一处理单元包括指令排序单元，执行单元，执行获取指令以获取全球促销设施内的特定促销位字段，以及促销意识设施。 响应于第一处理单元窥探特定促销位字段的第二处理单元的请求，第一处理单元在全局推广设备中记录第二处理单元和特定促销位字段之间的关联。 在由第一处理单元请求和释放特定促销位字段之后，第一处理单元检查促销感知设施以获得针对特定促销位的关联并且响应于检查，将特定促销位字段推送到第二处理 在所述互连上使用非请求操作的单元，使得不需要所述第二处理单元的附加请求。

公开(公告)号：US06963967B1

公开(公告)日：2005-11-08

申请号：US09588508

申请日：2000-06-06

申请人： Guy Lynn Guthrie ,  Ravi Kumar Arimilli ,  John Steven Dodson ,  Derek Edward Williams

发明人： Guy Lynn Guthrie ,  Ravi Kumar Arimilli ,  John Steven Dodson ,  Derek Edward Williams

IPC分类号： G06F9/00 ,  G06F9/30 ,  G06F9/38

CPC分类号： G06F9/3851 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/383 ,  G06F9/3834 ,  G06F9/3842 ,  G06F9/3861

摘要： Disclosed is a method of processing instructions in a data processing system. An instruction sequence that includes a memory access instruction is received at a processor in program order. In response to receipt of the memory access instruction a memory access request and a barrier operation are created. The barrier operation is placed on an interconnect after the memory access request is issued to a memory system. After the barrier operation has completed, the memory access request is completed in program order. When the memory access request is a load request, the load request is speculatively issued if a barrier operation is pending. Data returned by the speculatively issued load request is only returned to a register or execution unit of the processor when an acknowledgment is received for the barrier operation.

摘要翻译： 公开了一种在数据处理系统中处理指令的方法。 包括存储器访问指令的指令序列以处理器的顺序被接收。 响应于接收到存储器访问指令，创建存储器访问请求和屏障操作。 在将存储器访问请求发布到存储器系统之后，屏障操作被放置在互连上。 屏障操作完成后，按程序顺序完成内存访问请求。 当存储器访问请求是加载请求时，如果屏障操作正在等待，则推测性地发出加载请求。 当接收到用于屏障操作的确认时，由推测发出的加载请求返回的数据仅返回到处理器的寄存器或执行单元。

公开(公告)号：US06785774B2

公开(公告)日：2004-08-31

申请号：US09978362

申请日：2001-10-16

申请人： Ravi Kumar Arimilli ,  Guy Lynn Guthrie ,  William J. Starke ,  Derek Edward Williams

发明人： Ravi Kumar Arimilli ,  Guy Lynn Guthrie ,  William J. Starke ,  Derek Edward Williams

IPC分类号： G06F1200

CPC分类号： G06F12/0831

摘要： A multiprocessor data processing system comprising a plurality of processing units, a plurality of caches, that is each affiliated with one of the processing units, and processing logic that, responsive to a receipt of a first system bus response to a coherency operation, causes the requesting processor to execute operations utilizing super-coherent data. The data processing system further includes logic eventually returning to coherent operations with other processing units responsive to an occurrence of a pre-determined condition. The coherency protocol of the data processing system includes a first coherency state that indicates that modification of data within a shared cache line of a second cache of a second processor has been snooped on a system bus of the data processing system. When the cache line is in the first coherency state, subsequent requests for the cache line is issued as a Z1 read on a system bus and one of two responses are received. If the response to the Z1 read indicates that the first processor should utilize local data currently available within the cache line, the first coherency state is changed to a second coherency state that indicates to the first processor that subsequent request for the cache line should utilize the data within the local cache and not be issued to the system interconnect. Coherency state transitions to the second coherency state is completed via the coherency protocol of the data processing system. Super-coherent data is provided to the processor from the cache line of the local cache whenever the second coherency state is set for the cache line and a request is received.

摘要翻译： 一种多处理器数据处理系统，包括多个处理单元，多个高速缓存，每个高速缓存与每个处理单元中的一个相关联;以及处理逻辑，响应于对一致性操作的第一系统总线响应的接收，使得 请求处理器使用超相干数据执行操作。 数据处理系统还包括逻辑，其最终返回到响应于预定条件的发生的其他处理单元的相干操作。 数据处理系统的一致性协议包括第一相关性状态，其指示在数据处理系统的系统总线上已经窥探第二处理器的第二高速缓存的共享高速缓存行内的数据的修改。 当高速缓存行处于第一相关性状态时，在系统总线上作为Z1读取发出对高速缓存行的后续请求，并且接收到两个响应中的一个。 如果对Z1读取的响应指示第一处理器应利用高速缓存行内当前可用的本地数据，则将第一相关性状态改变为第二相关性状态，其向第一处理器指示对高速缓存行的后续请求应当利用 本地缓存内的数据，不发给系统互连。 通过数据处理系统的一致性协议完成一致性状态转换到第二相关性状态。 每当为高速缓存行设置第二相关性状态并接收到请求时，将超相干数据从本地高速缓存行提供给处理器。

公开(公告)号：US06609192B1

公开(公告)日：2003-08-19

申请号：US09588607

申请日：2000-06-06

申请人： Guy Lynn Guthrie ,  Ravi Kumar Arimilli ,  John Steven Dodson ,  Derek Edward Williams

发明人： Guy Lynn Guthrie ,  Ravi Kumar Arimilli ,  John Steven Dodson ,  Derek Edward Williams

IPC分类号： G06F9312

CPC分类号： G06F9/30087 ,  G06F9/3834 ,  G06F9/3842

摘要： Disclosed is a multiprocessor data processing system that executes loads transactions out of order with respect to a barrier operation. The data processing system includes a memory and a plurality of processors coupled to an interconnect. At least one of the processors includes an instruction sequencing unit for fetching an instruction sequence in program order for execution. The instruction sequence includes a first and a second load instruction and a barrier instruction, which is between the first and second load instructions in the instruction sequence. Also included in the processor is a load/store unit (LSU), which has a load request queue (LRQ) that temporarily buffers load requests associated with the first and second load instructions. The LRQ is coupled to a load request arbitration unit, which selects an order of issuing the load requests from the LRQ. Then a controller issues a load request associated with the second load instruction to memory before completion of a barrier operation associated with the barrier instruction. Alternatively, load requests are issued out-of-order with respect to the program order before or after the barrier instruction. The load request arbitration unit selects the request associated with the second load instruction before a request associated with the first load instruction, and the controller issues the request associated with the second load instruction before the request associated with the first load instruction and before issuing the barrier operation.

摘要翻译： 公开了一种多处理器数据处理系统，其针对屏障操作执行无序的负载事务。 数据处理系统包括存储器和耦合到互连的多个处理器。 至少一个处理器包括用于以程序顺序取出指令序列以执行的指令排序单元。 指令序列包括在指令序列中的第一和第二加载指令之间的第一和第二加载指令和障碍指令。 还包括在处理器中的是装载/存储单元（LSU），其具有临时缓冲与第一和第二加载指令相关联的加载请求的加载请求队列（LRQ）。 LRQ耦合到负载请求仲裁单元，该单元从LRQ中选择发出负载请求的顺序。 然后，在与障碍指令相关联的屏障操作完成之前，控制器向存储器发出与第二加载指令相关联的加载请求。 或者，负载请求在屏障指令之前或之后相对于程序顺序发出无序。 负载请求仲裁单元在与第一加载指令相关联的请求之前选择与第二加载指令相关联的请求，并且控制器在与第一加载指令相关联的请求之前发布与第二加载指令相关联的请求，并且在发布屏障之前 操作。

公开(公告)号：US06430586B1

公开(公告)日：2002-08-06

申请号：US09328304

申请日：1999-06-08

申请人： Derek Edward Williams

发明人： Derek Edward Williams

IPC分类号： G06F102

CPC分类号： G06F11/2215 ,  G01R31/318385 ,  G06F7/58

摘要： A controllable bit stream generator for providing a random bit source with a desired probability. The controllable bit stream generator comprises a digital component which generates a pseudo-random bit sequence, a variable probability conditioner coupled to the digital component and which accepts the pseudo-random bit sequence and outputs a corresponding controlled output, and a register coupled to the variable probability conditioner. The register is utilized to send a control signal to the variable probability conditioner. The controllable bit stream generator creates a random output bit sequence for the controlled output utilizing the variable probability conditioner and the control signal of the register.

摘要翻译： 一种可控比特流发生器，用于提供具有所需概率的随机比特源。 可控比特流生成器包括产生伪随机比特序列的数字分量，耦合到数字分量的可变概率调节器，并接收伪随机比特序列并输出对应的受控输出，以及耦合到该变量的寄存器 概率调理剂 该寄存器用于向可变概率调节器发送控制信号。 可控位流发生器利用可变概率调节器和寄存器的控制信号来产生用于受控输出的随机输出位序列。

公开(公告)号：US06292908B1

公开(公告)日：2001-09-18

申请号：US09175391

申请日：1998-10-19

申请人： Ravi Kumar Arimilli ,  Keenan Wynn Franz ,  David B. Shuler ,  Derek Edward Williams

发明人： Ravi Kumar Arimilli ,  Keenan Wynn Franz ,  David B. Shuler ,  Derek Edward Williams

IPC分类号： G06F1130

CPC分类号： G06F11/364 ,  G06F11/349

摘要： An apparatus and method for monitoring an internal communication path, i.e. an internal bus, of an integrated circuit is described. The internal bus operates at a particular frequency, fb. An image of the internal bus is produced, operating at a lower frequency of operations, fo, which is more amenable to monitoring by test equipment. Signals are received from and driven to the bus using driver/receiver circuitry. The signals may be input-only, output-only, or bi-directional signals. The signals to be monitored are tapped in the driver/receiver circuitry. Depending on the placement of the signal taps in the driver/receiver logic, the signals may be “out-of-phase” with respect to one another. A buffer/align unit processes the signals in order to produce a time delayed version of the signals. The buffer/aliqn unit is used to bring each of the monitored signals back in phase relative to one another. Encoding circuitry encodes the time delayed version of the bus in a manner that produces an image of the bus at the lower frequency of operations, fo. The encoding circuitry considers the values of the monitored signals over an encoding window, and produces an encoded value for each signal at the lower frequency of operations, fo.

摘要翻译： 描述了用于监视集成电路的内部通信路径即内部总线的装置和方法。 内部总线以特定频率fb运行。 生产内部总线的图像，操作频率较低，更适合于测试设备的监控。 使用驱动器/接收器电路从信号接收和驱动到总线。 信号可以是仅输入信号，仅输出信号或双向信号。 要监视的信号被点击在驱动器/接收器电路中。 根据驱动器/接收器逻辑中的信号抽头的布置，信号可能相对于彼此“异相”。 缓冲器/对准单元处理信号以产生信号的时间延迟版本。 缓冲器/ aliqn单元用于使每个被监控的信号相对于彼此反相。 编码电路以以更低的操作频率fo产生总线的图像的方式对总线的时间延迟版本进行编码。 编码电路在编码窗口中考虑监视信号的值，并且以较低的操作频率fo产生每个信号的编码值。