公开(公告)号：US06610924B1

公开(公告)日：2003-08-26

申请号：US09625023

申请日：2000-07-25

申请人： Shih-Chang Lee ,  Su Tao

发明人： Shih-Chang Lee ,  Su Tao

IPC分类号： H01L2302

CPC分类号： H01L23/544 ,  H01L23/3107 ,  H01L23/49548 ,  H01L24/48 ,  H01L2223/54473 ,  H01L2224/05599 ,  H01L2224/32245 ,  H01L2224/45099 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012

摘要： A semiconductor package has a semiconductor chip disposed on a die pad and electrically connected to a plurality of leads arranged around the die pad. There are a plurality of tie bars connected to the die pad. Each tie bar extends from a corner of the die pad to a corresponding corner of the leadless semiconductor package. The semiconductor chip, the leads and the tie bars are encapsulated in a package body wherein the backside surface of the leads is exposed from the lower surface of the semiconductor package. All the tie bars of the semiconductor package are embedded in the package body except a part of at least one tie bar or an odd number of tie bars exposed from the lower surface of the semiconductor package to work as an indicial mark.

摘要翻译： 半导体封装具有设置在管芯焊盘上的半导体芯片，并且电连接到围绕管芯焊盘布置的多个引线。 存在连接到管芯焊盘的多个连接杆。 每个连接杆从芯片焊盘的角延伸到无引线半导体封装的相应角部。 半导体芯片，引线和连接条被封装在封装主体中，其中引线的背面从半导体封装的下表面露出。 半导体封装的所有连接条都嵌入在封装主体中，除了从半导体封装的下表面暴露的至少一个连接条或奇数个连接条的一部分作为指示标记之外。

公开(公告)号：US06573123B2

公开(公告)日：2003-06-03

申请号：US10029845

申请日：2001-12-31

申请人： Sai Man Li ,  Chun Hung Lin ,  Shin Hua Chao ,  Su Tao

发明人： Sai Man Li ,  Chun Hung Lin ,  Shin Hua Chao ,  Su Tao

IPC分类号： H01L2144

CPC分类号： H01L21/568 ,  H01L23/3107 ,  H01L2224/45144 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00 ,  H01L2924/00012

摘要： A semiconductor chip package generally comprises a lead frame, a semiconductor die and a plastic package body. The lead frame includes a plurality of leads and a window pad. The window pad is connected to the lead frame by connecting bars. The inner ends of the plurality of leads defines a central area. The window pad is disposed in the central area and has an opening defined therein. The semiconductor die is disposed in the opening of the window pad and has a plurality of bonding pads formed on the active surface thereof. The inner ends of the leads are interconnected to the bonding pads on the semiconductor die through a plurality of bonding wires. The lead frame, the semiconductor die and the bonding wires are encapsulated in the plastic package body wherein the lower surface of the lead frame and the backside surface of the semiconductor die are exposed through the plastic package body.

公开(公告)号：US06313413B1

公开(公告)日：2001-11-06

申请号：US09414584

申请日：1999-10-08

申请人： Kun-Ching Chen ,  Yire-Zine Lee ,  Yung-I Yeh ,  Su Tao

发明人： Kun-Ching Chen ,  Yire-Zine Lee ,  Yung-I Yeh ,  Su Tao

IPC分类号： H05K111

CPC分类号： H01L23/49838 ,  H01L23/13 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/4824 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： The substrate of the present invention mainly includes a plurality of bonding pads, a plurality of ball pads, a plurality of traces, a plurality of holes, a first wire and a second wire. The bonding pads and ball pads are located on a first surface of the substrate and are connected to one another by the traces. The first wire is arranged at the edge of the first surface of the substrate, the second wire is arranged at a slot area of a second surface of the substrate which is adhesively covered by a solder mask and further has two ends connecting to the first wire. The holes connect the first surface to the second surface. The traces are connected the bonding pads and ball pads of the first surface by passing through the corresponding holes and a slot area to the second wire of the second surface to form closed loops. In the slot area, the solder mask adhesively covers the traces. During the slot sawing processes of the slot area, some parts of the traces in the slot area and the second wire are cut to form an opened loop. Then the ends of the traces at the edge of the slot area have little lateral malleability. Thus the adjacent ends of traces cannot be connected to one another; so the substrate of the present invention can use the socket of the test machine to increase efficiency.

摘要翻译： 本发明的基板主要包括多个接合焊盘，多个焊盘，多个焊盘，多个孔，第一焊丝和第二焊丝。 接合焊盘和焊盘位于衬底的第一表面上，并通过迹线彼此连接。 第一线布置在基板的第一表面的边缘处，第二布线布置在基板的第二表面的狭缝区域，该第二表面被焊接掩模粘合，并且还具有连接到第一布线的两个端部 。 孔将第一表面连接到第二表面。 迹线通过穿过对应的孔和槽区域连接到第一表面的接合焊盘和球焊盘到第二表面的第二线，以形成闭环。 在插槽区域，焊接掩模粘合地覆盖迹线。 在缝隙区域的槽锯工艺过程中，槽区域中的迹线的一些部分和第二线被切割以形成开环。 然后在狭槽区域的边缘处的迹线的端部具有很小的侧向延展性。 因此，迹线的相邻端不能彼此连接; 因此本发明的基板可以使用试验机的插座来提高效率。

公开(公告)号：US06215193B1

公开(公告)日：2001-04-10

申请号：US09295342

申请日：1999-04-21

申请人： Su Tao ,  Meng-Hui Lin

发明人： Su Tao ,  Meng-Hui Lin

IPC分类号： H01L2348

CPC分类号： H01L25/0657 ,  H01L24/48 ,  H01L24/49 ,  H01L29/0657 ,  H01L2224/05554 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49112 ,  H01L2224/49175 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2225/06575 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/014 ,  H01L2924/10155 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： A multichip module includes a substrate having two padding strips, a first chip, and a second chip mounted thereon. The padding strips are mounted to two sides of the first chip. The second chip is disposed above the first chip in a manner that the bonding pads of the first chip are exposed outside the lateral edges of the second chip. In another embodiment of the invention, the substrate includes a recess, a first chip, and a second chip. The first chip is received in the first chip, and the second chip is disposed above the first chip in a manner that the bonding pads of the first chip are exposed outside the lateral edges of the second chip. A method is provided to manufacture a multichip module by placing a first chip on a substrate and then placing a second chip above the first chip in a manner that the bonding pads of the first chip are exposed outside the lateral edges of the second chip.

摘要翻译： 多芯片模块包括具有两个衬垫条的衬底，第一芯片和安装在其上的第二芯片。 填充条安装在第一芯片的两侧。 第二芯片以第一芯片的焊盘暴露在第二芯片的侧边缘外侧的方式设置在第一芯片上方。 在本发明的另一个实施例中，衬底包括凹槽，第一芯片和第二芯片。 第一芯片被接收在第一芯片中，并且第二芯片以第一芯片的焊盘暴露在第二芯片的横向边缘的方式设置在第一芯片上方。 提供了一种通过将第一芯片放置在基板上，然后以第一芯片的焊盘暴露在第二芯片的横向边缘外的方式将第二芯片放置在第一芯片上方的方法来制造多芯片模块。

公开(公告)号：US06190529B1

公开(公告)日：2001-02-20

申请号：US09294929

申请日：1999-04-19

申请人： Yei-Shen Wu ,  Kun-Ching Chen ,  Su Tao

发明人： Yei-Shen Wu ,  Kun-Ching Chen ,  Su Tao

IPC分类号： C25D502

CPC分类号： H01L24/86 ,  C25D7/12 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014

摘要： A method for plating gold to a plurality of bond leads on a substrate is disclosed. The method first extends a plating line from a plating loop on the edge of the substrate to a bond area in the center portion of the substrate to electrically connect the plurality of bond leads in series. The plating line further extends to connect to the plating loop after connecting the plurality of bond leads together. Then, electricity is applied to the plurality of bond leads via the plating loop and the plating line thereby plates gold to the plurality of bond leads. Finally, a bonding tool is used to cut off and remove the plating line when the bonding tool is provided to bond the plurality of bond leads to a die that is attached to the substrate, whereby the residual plating line remaining on the substrate does not affect the performance of the semiconductor chip.

摘要翻译： 公开了一种将金镀在基板上的多个键合引线上的方法。 该方法首先将电镀线从衬底的边缘上的电镀环延伸到衬底的中心部分的结合区域，以将多个接合引线串联电连接。 在将多个接合引线连接在一起之后，电镀线还延伸以连接到电镀回路。 然后，通过电镀回路和电镀线向多个接合引线施加电力，由此向多个接合引线镀金。 最后，当提供接合工具以将多个接合引线连接到附接到基板的管芯上时，使用接合工具来切断和移除电镀线，由此残留在基板上的残余电镀线不会影响 半导体芯片的性能。