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    Single event upset (SEU) hardened static random access memory cell
    91.
    发明授权
    Single event upset (SEU) hardened static random access memory cell 有权
    单事件镦粗（SEU）硬化静态随机存取存储单元

    公开(公告)号：US06259643B1

    公开(公告)日：2001-07-10

    申请号：US09651155

    申请日：2000-08-30

    Applicant: Bin Li

    Inventor： Bin Li

    IPC: G11C702

    CPC classification number: G11C11/4125

    Abstract: A single event effect hardening technique for removing glitches in digital logic circuits is disclosed. The noise immune latch circuit includes a first input, a second input, and an output. The noise immune latch circuit includes a first set of two cross-coupled transistors, a second set of two cross-coupled transistors, a first set of isolation transistors, and a second set of isolation transistors. The cross-coupling is accomplished by connecting a gate of each transistor to a drain of another transistor in a same set. The first and second sets of isolation transistors are respectively connected to the first and second sets of cross-coupled transistors such that two inversion paths are formed including the two sets of cross-coupled transistors and the two sets of isolation transistors. The noise immune latch circuit changes from one state to another state only upon having incoming input signals of identical polarity being applied contemporaneously at both the first input and the second input. In addition, a delay element is connected between the incoming signals and the second input. The delay element provides a signal delay time equal to or greater than a pulse width of a noise induced glitch but less than a pre-determined pulse width of an incoming signal under normal operation.

    Abstract translation: 公开了用于消除数字逻辑电路中的毛刺的单一事件效应强化技术。 噪声免疫锁定电路包括第一输入端，第二输入端和输出端。 噪声免疫锁存电路包括第一组两个交叉耦合晶体管，第二组两个交叉耦合晶体管，第一组隔离晶体管和第二组隔离晶体管。 交叉耦合是通过将每个晶体管的栅极连接到同一组中的另一个晶体管的漏极来实现的。 第一和第二组隔离晶体管分别连接到第一和第二组交叉耦合晶体管，使得形成包括两组交叉耦合晶体管和两组隔离晶体管的两个反转路径。 噪声免疫锁定电路仅在具有相同极性的输入输入信号同时在第一输入端和第二输入端施加时，从一种状态变化到另一状态。 此外，延迟元件连接在输入信号和第二输入之间。 延迟元件提供等于或大于噪声感应毛刺的脉冲宽度但小于在正常操作下的输入信号的预定脉冲宽度的信号延迟时间。

    Electric power-assisted bicycle
    92.
    发明授权
    Electric power-assisted bicycle 失效
    电动辅助自行车

    公开(公告)号：US06152249A

    公开(公告)日：2000-11-28

    申请号：US199585

    申请日：1998-11-25

    Applicant: Ke Mei Li ,  Wen Shi Wang ,  Bin Li ,  Qing Zhu

    Inventor： Ke Mei Li ,  Wen Shi Wang ,  Bin Li ,  Qing Zhu

    IPC: B62M6/65 ,  B62M6/55 ,  B62K11/00

    CPC classification number: B62M6/55

    Abstract: A kind of electric power-assisted bicycle is presented in the invention. Its characters consist in that: the electric-driving device 2 is composed of the flat motor installed in the shell and harmonic reducer; the shell body and storage battery are fixed in the middle of the frame; its center shaft crosses the flat motor and the harmonic reducer along with the axis line separately, and can rotate relatively to them; the mentioned flat motor is connected with the power-transmitting device through the harmonic reducer. The entire bicycle is lightweight and long-life, while it is also energy saving high efficient and can be conveniently assembled, used, carried and maintained.

    Abstract translation: 本发明提出了一种电动辅助自行车。 其特征在于：电驱动装置2由安装在外壳中的扁平电机和谐波减速器组成; 壳体和蓄电池固定在框架的中间; 其中心轴分别与平面电机和谐波减速器一起穿过轴线，并可相对于它们旋转; 所述扁平电动机通过谐波减速器与发电装置连接。 整个自行车重量轻，使用寿命长，同时节能高效，方便组装，使用，携带和维护。

    Coded-block-flag coding and derivation
    96.
    发明授权
    Coded-block-flag coding and derivation 有权

    公开(公告)号：US09749645B2

    公开(公告)日：2017-08-29

    申请号：US13530849

    申请日：2012-06-22

    Applicant: Bin Li ,  Jizheng Xu

    Inventor： Bin Li ,  Jizheng Xu

    IPC: H04N7/12 ,  H04N19/18 ,  H04N19/96 ,  H04N19/463 ,  H04N19/132

    CPC classification number: H04N19/18 ,  H04N19/132 ,  H04N19/463 ,  H04N19/96

    Abstract: Techniques for coding and deriving (e.g., determining) one or more coded-block-flags associated with video content are described herein. A coded-block-flag of a last node may be determined when coded-block-flags of preceding nodes are determined to be a particular value and when a predetermined condition is satisfied. In some instances, the predetermined condition may be satisfied when log2(size of current transform unit) is less than log2(size of maximum transform unit) or log2(size of current coding unit) is less than or equal to log2(size of maximum transform unit)+1. The preceding nodes may be nodes that precede the last node on a particular level in a residual tree.

    UNIFIED INTRA BLOCK COPY AND INTER PREDICTION MODES
    98.
    发明申请
    UNIFIED INTRA BLOCK COPY AND INTER PREDICTION MODES 审中-公开

    公开(公告)号：US20170142418A1

    公开(公告)日：2017-05-18

    申请号：US15319797

    申请日：2014-06-19

    Applicant: Bin LI ,  Ji-Zheng XU ,  Microsoft Technology Licensing, LLC

    Inventor： Bin Li ,  Ji-Zheng Xu

    IPC: H04N19/159 ,  H04N19/184 ,  H04N19/176 ,  H04N19/513 ,  H04N19/174

    Abstract: Innovations in unified intra block copy (“BC”) and inter prediction modes are presented. In some example implementations, bitstream syntax, semantics of syntax elements and many coding/decoding processes for inter prediction mode are reused or slightly modified to enable intra BC prediction for blocks of a frame. For example, to provide intra BC prediction for a current block of a current picture, a motion compensation process applies a motion vector that indicates a displacement within the current picture, with the current picture being used as a reference picture for the motion compensation process. With this unification of syntax, semantics and coding/decoding processes, various coding/decoding tools designed for inter prediction mode, such as advanced motion vector prediction, merge mode and skip mode, can also be applied when intra BC prediction is used, which simplifies implementation of intra BC prediction.

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