公开(公告)号：US08446782B2

公开(公告)日：2013-05-21

申请号：US13271645

申请日：2011-10-12

申请人： Hiroyuki Nagashima ,  Naoya Tokiwa

发明人： Hiroyuki Nagashima ,  Naoya Tokiwa

IPC分类号： G11C8/08

摘要： A semiconductor memory device comprises a plurality of memory layers arranged in multilayer, each memory layer including a cell array, the cell array containing a plurality of first parallel lines, a plurality of second parallel lines arranged crossing the first lines, and a plurality of memory cells connected at intersections of the first lines and the second lines; a pulse generator operative to generate pulses required for data access to the memory cell; and a control means operative to control the pulse generator such that the pulse output from the pulse generator has energy in accordance with the memory layer to which the access target memory cell belongs.

公开(公告)号：US08391082B2

公开(公告)日：2013-03-05

申请号：US13099540

申请日：2011-05-03

申请人： Hiroyuki Nagashima ,  Hirofumi Inoue

发明人： Hiroyuki Nagashima ,  Hirofumi Inoue

IPC分类号： G11C7/10

CPC分类号： G11C13/0069 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1075 ,  G11C7/22 ,  G11C8/16 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0061 ,  G11C13/0097 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2216/24

摘要： A nonvolatile semiconductor memory device comprises a cell array including plural MATs (unit cell arrays) arranged in matrix, each MAT containing a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells connected at intersections of the first and second lines between both lines, each memory cell containing an electrically erasable programmable variable resistive element of which resistance is stored in a non-volatile manner as data; and a plurality of write/erase circuits connected to the MATs and operative to execute data write or erase to the memory cells inside the MATs in accordance with input data. A part of the plurality of write/erase circuits writes data to memory cells inside a corresponding MAT while another part of the plurality of write/erase circuits erases data from memory cells inside a corresponding MAT at the same time.

摘要翻译： 一种非易失性半导体存储器件，包括一个单元阵列，该单元阵列包括矩阵排列的多个MAT（单元阵列），每个MAT包含多条第一线，与该多条第一线交叉的多条第二线，以及多条存储单元 两行之间的第一和第二行的交点，每个存储单元包含以电阻作为数据以非易失性方式存储的电可擦除可编程可变电阻元件; 以及多个写入/擦除电路，连接到MAT，并根据输入数据对MAT内的存储单元执行数据写入或擦除。 多个写/擦除电路的一部分将数据写入相应MAT内的存储单元，而多个写/擦除电路的另一部分同时从相应MAT内的存储单元擦除数据。

公开(公告)号：US08363472B2

公开(公告)日：2013-01-29

申请号：US12690500

申请日：2010-01-20

申请人： Hiroyuki Nagashima

发明人： Hiroyuki Nagashima

IPC分类号： H01L27/10

CPC分类号： H01L27/04 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/06 ,  H01L45/085 ,  H01L45/10 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1675

摘要： A non-volatile semiconductor memory device includes: a cell array including a plurality of first wirings, a plurality of second wirings that intersects the plurality of first wirings, and memory cells that are formed at intersections of the first wirings and the second wirings and are connected between the first and second wirings; a first contact plug that comes into contact with a side portion of the first wiring provided at a first position and extends to the first wiring provided at a second position higher than the first position in a laminated direction; and a second contact plug that comes into contact with a side portion of the second wiring provided at a third position between the first position and the second position and extends to the second wiring provided at a fourth position higher than the second position in the laminated direction.

摘要翻译： 非易失性半导体存储器件包括：包括多个第一布线的多个第一布线，与多个第一布线相交的多个第二布线，以及形成在第一布线和第二布线的交叉处的存储单元的单元阵列， 连接在第一和第二布线之间; 第一接触插塞，其与设置在第一位置处的第一布线的侧部接触并且延伸到设置在高于第一位置的层叠方向的第二位置处的第一布线; 以及第二接触插塞，其与设置在第一位置和第二位置之间的第三位置处的第二配线的侧部接触，并且延伸到设置在高于第二位置的层叠方向上的第四位置处的第二配线 。

公开(公告)号：US07957203B2

公开(公告)日：2011-06-07

申请号：US12511443

申请日：2009-07-29

申请人： Hiroyuki Nagashima ,  Hirofumi Inoue

发明人： Hiroyuki Nagashima ,  Hirofumi Inoue

IPC分类号： G11C7/10

CPC分类号： G11C13/0069 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/1075 ,  G11C7/22 ,  G11C8/16 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0061 ,  G11C13/0097 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/31 ,  G11C2213/72 ,  G11C2216/24

摘要： A nonvolatile semiconductor memory device comprises a cell array including plural MATs (unit cell arrays) arranged in matrix, each MAT containing a plurality of first lines, a plurality of second lines intersecting the plurality of first lines, and a plurality of memory cells connected at intersections of the first and second lines between both lines, each memory cell containing an electrically erasable programmable variable resistive element of which resistance is nonvolatilely stored as data; and a plurality of write/erase circuits connected to the MATs and operative to execute data write or erase to the memory cells inside the MATs in accordance with input data. A part of the plurality of write/erase circuits writes data to memory cells inside a corresponding MAT while another part of the plurality of write/erase circuits erases data from memory cells inside a corresponding MAT at the same time.

摘要翻译： 一种非易失性半导体存储器件，包括一个单元阵列，该单元阵列包括矩阵排列的多个MAT（单元阵列），每个MAT包含多条第一线，与该多条第一线交叉的多条第二线，以及多条存储单元 两行之间的第一和第二行的交点，每个存储单元包含电可擦除可编程可变电阻元件，其电阻被非挥发性地存储为数据; 以及多个写入/擦除电路，连接到MAT，并根据输入数据对MAT内的存储单元执行数据写入或擦除。 多个写/擦除电路的一部分将数据写入相应MAT内的存储单元，而多个写/擦除电路的另一部分同时从相应MAT内的存储单元擦除数据。

公开(公告)号：US07952931B2

公开(公告)日：2011-05-31

申请号：US12132426

申请日：2008-06-03

申请人： Hiroyuki Nagashima ,  Koki Ueno

发明人： Hiroyuki Nagashima ,  Koki Ueno

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/10 ,  G11C16/12

摘要： A nonvolatile semiconductor memory device includes a memory cell array having a plurality of cell units each including a preset number of memory cells and select gate transistors on drain and source sides. The nonvolatile semiconductor memory device includes a voltage control circuit to prevent occurrence of an erroneous write operation due to excessively high boost voltage of a channel when “1” is written into the memory cell.

摘要翻译： 非易失性半导体存储器件包括具有多个单元单元的存储单元阵列，每个单元单元包括预设数量的存储单元和漏极和源极侧的选择栅极晶体管。 非易失性半导体存储器件包括电压控制电路，用于当“1”被写入存储器单元时，防止由于通道的过高的升压电压而导致的错误写入操作的发生。

公开(公告)号：US20100211725A1

公开(公告)日：2010-08-19

申请号：US12672083

申请日：2008-10-17

申请人： Hiroyuki Nagashima ,  Hiroto Nakai

发明人： Hiroyuki Nagashima ,  Hiroto Nakai

IPC分类号： G06F12/00 ,  G06F12/08 ,  G11C11/00

CPC分类号： G11C13/0069 ,  G06F12/0246 ,  G06F12/0893 ,  G11C11/005 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0033 ,  G11C16/3431 ,  G11C2213/11 ,  G11C2213/31 ,  G11C2213/34 ,  G11C2213/56 ,  G11C2213/72

摘要： An information processing system comprises a main memory operative to store data, and a control circuit operative to access the main memory for data. The main memory includes a nonvolatile semiconductor memory device containing electrically erasable programmable nonvolatile memory cells each using a variable resistor, and a DRAM arranged as a cache memory between the control circuit and the nonvolatile semiconductor memory device. The nonvolatile semiconductor memory device has a refresh mode of rewriting stored data. The control circuit activates the nonvolatile semiconductor memory device in said refresh mode based on the number of accesses to the nonvolatile semiconductor memory device.

摘要翻译： 信息处理系统包括可操作地存储数据的主存储器和可操作以访问主存储器以用于数据的控制电路。 主存储器包括：非易失性半导体存储器件，其包含电可擦除的可编程非易失性存储单元，每个可擦除可编程非易失性存储单元使用可变电阻器;以及DRAM，其布置在控制电路和非易失性半导体存储器件 非易失性半导体存储器件具有重写存储数据的刷新模式。 控制电路基于对非易失性半导体存储器件的访问次数，在所述刷新模式下激活非易失性半导体存储器件。

公开(公告)号：US20090268521A1

公开(公告)日：2009-10-29

申请号：US12397808

申请日：2009-03-04

申请人： Koki Ueno ,  Hiroyuki Nagashima

发明人： Koki Ueno ,  Hiroyuki Nagashima

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/349 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0483 ,  G11C29/028 ,  G11C29/50 ,  G11C29/82 ,  G11C2029/5006 ,  G11C2211/565

摘要： A non-volatile semiconductor memory device includes a non-volatile memory having a plurality of blocks each including a plurality of memory cells, a bit line electrically connected to one end of a current path of the memory cell, a source line electrically connected to the other end of the current path of the memory cell, a word line electrically connected to the gate electrode, a sense amplifier circuit electrically connected to the bit line and configured to read data from the memory cell, a row decoder electrically connected to the word line and configured to apply a read voltage at which the memory cell is set to an ON state to the word line, and a controller configured to measure a cell current flowing through the memory cell in the ON state to judge whether the memory cell has been degraded.

摘要翻译： 非挥发性半导体存储器件包括具有多个块的非易失性存储器，每个块包括多个存储器单元，电连接到存储单元的电流路径的一端的位线，电连接到存储单元的源极线 存储单元的电流路径的另一端，电连接到栅电极的字线，电连接到位线并被配置为从存储单元读取数据的读出放大器电路，电连接到字线的行解码器 并且被配置为将存储单元设置为ON状态的读取电压施加到字线，以及控制器，被配置为测量在ON状态下流过存储单元的单元电流，以判断存储单元是否已经劣化 。

公开(公告)号：US07603053B2

公开(公告)日：2009-10-13

申请号：US11736881

申请日：2007-04-18

申请人： Hiroshi Hosokawa ,  Hiroyuki Nagashima ,  Nobuo Kuwabara ,  Hirotaka Hatta

发明人： Hiroshi Hosokawa ,  Hiroyuki Nagashima ,  Nobuo Kuwabara ,  Hirotaka Hatta

IPC分类号： G03G15/08

CPC分类号： G03G15/0882 ,  G03G2215/0687

摘要： A development device that has communication port sealing means for sealing a communication port communicating a developer supporter container with a developer container. The development device is advantageous in cost reduction, easy manufacturing, and formation of high-quality images. In the development device which has a developing roller container for containing a developing roller, a developer container for containing a developer, a base member for forming a communication port communicating the developer roller container with the developer container, and a seal member that is adhered to the base member so as to cover the communication port, and which cancels sealing of the communication port by peeling off the seal member from the base member by pulling out the seal member in a direction parallel to an opened surface of the communication port, the base member is composed of a polypropylene resin having a bent section, and the seal member is adhered to the base member by thermal compression bonding.

摘要翻译： 一种开发装置，具有用于密封将显影剂载体容器与显影剂容器连通的通信口的通信口密封装置。 显影装置在成本降低，易于制造和形成高质量图像方面是有利的。 在具有用于容纳显影辊的显影辊容器的显影装置中，用于容纳显影剂的显影剂容器，用于形成使显影剂辊容器与显影剂容器连通的连通口的基底部件和粘附到 所述基座部件覆盖所述连通口，并且通过在与所述连通口的开口面平行的方向上拉出所述密封部件而从所述基部部件剥离所述密封部件来抵消所述连通口的密封，所述基部 构件由具有弯曲部分的聚丙烯树脂构成，并且密封构件通过热压接而粘附到基底构件。

公开(公告)号：US20090022504A1

公开(公告)日：2009-01-22

申请号：US12175788

申请日：2008-07-18

申请人： Nobuo KUWABARA ,  Masahiko Satoh ,  Noriyuki Kimura ,  Eisuke Hori ,  Hideki Kimura ,  Hiroyuki Nagashima ,  Hiroshi Ono ,  Masahiko Shakuto

发明人： Nobuo KUWABARA ,  Masahiko Satoh ,  Noriyuki Kimura ,  Eisuke Hori ,  Hideki Kimura ,  Hiroyuki Nagashima ,  Hiroshi Ono ,  Masahiko Shakuto

IPC分类号： G03G15/00

CPC分类号： H04N1/00326 ,  B41J29/393 ,  G03G21/1896 ,  H04N1/00334

摘要： An image forming apparatus includes a unit, a mark detector, and a controller. The unit is attachable to and detachable from the image forming apparatus and includes an information mark pattern indicating predetermined information. The mark detector detects the information mark pattern. The controller obtains the information indicated by the information mark pattern based on a detection result provided by the mark detector.

摘要翻译： 图像形成装置包括单元，标记检测器和控制器。 该单元可附接到图像形成装置并且可从该图像形成装置拆卸，并且包括指示预定信息的信息标记图案。 标记检测器检测信息标记图案。 控制器基于由标记检测器提供的检测结果获得由信息标记图案指示的信息。

公开(公告)号：US20070279983A1

公开(公告)日：2007-12-06

申请号：US11754574

申请日：2007-05-29

申请人： Hiroyuki Nagashima

发明人： Hiroyuki Nagashima

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C16/22

摘要： A semiconductor memory device includes a nonvolatile memory which stores protect information, a controller which includes a system buffer and controls a physical state of the nonvolatile memory, a battery which drives the nonvolatile memory and the controller, first transmission/reception means capable of transmitting data in the nonvolatile memory to an outside and receiving data which is transmitted from the outside, and second transmission/reception means capable of transmitting data in the nonvolatile memory to an outside and receiving data which is transmitted from the outside.

摘要翻译： 半导体存储器件包括存储保护信息的非易失性存储器，包括系统缓冲器并控制非易失性存储器的物理状态的控制器，驱动非易失性存储器和控制器的电池，能够发送数据的第一发送/接收装置 在外部的非易失性存储器中并且接收从外部发送的数据，以及能够将非易失性存储器中的数据发送到外部并接收从外部发送的数据的第二发送/接收装置。