公开(公告)号：US20120303871A1

公开(公告)日：2012-11-29

申请号：US13428089

申请日：2012-03-23

申请人： Naoya TOKIWA

发明人： Naoya TOKIWA

IPC分类号： G06F12/02

CPC分类号： G11C29/44 ,  G11C13/0004 ,  G11C13/0007 ,  G11C2029/4402

摘要： According to one embodiment, a semiconductor memory device includes a memory cell array including a plurality of memory cells, a first register configured to store data of the memory cells, and a sequence control circuit configured to control the memory cell array and the first register. In at least a data read operation of the memory cells, the sequence control circuit reads out, from the memory cell array, data including flag information representing whether the number of failed bits is in an allowable range.

摘要翻译： 根据一个实施例，半导体存储器件包括存储单元阵列，该存储单元阵列包括多个存储器单元，第一寄存器，被配置为存储存储单元的数据;以及序列控制电路，被配置为控制存储单元阵列和第一寄存器。 在存储器单元的至少一个数据读取操作中，顺序控制电路从存储单元阵列读出包括表示故障位数是否在允许范围内的标志信息的数据。

公开(公告)号：US20120113719A1

公开(公告)日：2012-05-10

申请号：US13353047

申请日：2012-01-18

申请人： Naoya Tokiwa

发明人： Naoya Tokiwa

IPC分类号： G11C16/06

CPC分类号： G11C16/06

摘要： A nonvolatile semiconductor storage device is disclosed, which includes a memory cell array in which nonvolatile memory cells are arranged, a first data holding circuit which temporarily holds a collective processing unit of read or write data to be simultaneously read from or written to the memory cells, a circuit which takes out the data held in the first data holding circuit from the device, and a second data holding circuit in which data is automatically set at a time when power supply is turned on and in which the data is changeable based on a command input to the device, wherein the collective processing unit is equal to a sum of the number of units used within the device and the maximum number of units continuously output from the device to outside or input to the device from outside.

摘要翻译： 公开了一种非易失性半导体存储装置，其包括其中布置非易失性存储器单元的存储单元阵列，暂时保持要同时从存储单元读取或写入存储单元的读或写数据的集合处理单元的第一数据保持电路 ，从设备取出保存在第一数据保持电路中的数据的电路，以及第二数据保持电路，其中在电源接通时自动设置数据，并且其中数据可基于 命令输入到所述设备，其中所述集体处理单元等于在所述设备内使用的单元数量与从所述设备连续输出到所述设备的外部或从外部输入到所述设备的单元的最大数量之和。

公开(公告)号：US08120957B2

公开(公告)日：2012-02-21

申请号：US12957466

申请日：2010-12-01

申请人： Naoya Tokiwa

发明人： Naoya Tokiwa

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/06

摘要： A nonvolatile semiconductor storage device is disclosed, which includes a memory cell array in which nonvolatile memory cells are arranged, a first data holding circuit which temporarily holds a collective processing unit of read or write data to be simultaneously read from or written to the memory cells, a circuit which takes out the data held in the first data holding circuit from the device, and a second data holding circuit in which data is automatically set at a time when power supply is turned on and in which the data is changeable based on a command input to the device, wherein the collective processing unit is equal to a sum of the number of units used within the device and the maximum number of units continuously output from the device to outside or input to the device from outside.

摘要翻译： 公开了一种非易失性半导体存储装置，其包括其中布置非易失性存储器单元的存储单元阵列，暂时保持要同时从存储单元读取或写入存储单元的读或写数据的集合处理单元的第一数据保持电路 ，从设备取出保存在第一数据保持电路中的数据的电路，以及第二数据保持电路，其中在电源接通时自动设置数据，并且其中数据可基于 命令输入到所述设备，其中所述集体处理单元等于在所述设备内使用的单元数量与从所述设备连续输出到所述设备的外部或从外部输入到所述设备的单元的最大数量之和。

公开(公告)号：US20110103135A1

公开(公告)日：2011-05-05

申请号：US13005582

申请日：2011-01-13

申请人： Toshiaki EDAHIRO ,  Kazushige Kanda ,  Naoya Tokiwa ,  Takuya Futatsuyama ,  Koji Hosono ,  Shigeo Ohshima

发明人： Toshiaki EDAHIRO ,  Kazushige Kanda ,  Naoya Tokiwa ,  Takuya Futatsuyama ,  Koji Hosono ,  Shigeo Ohshima

IPC分类号： G11C11/00

CPC分类号： H01L27/101 ,  G11C13/0007 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/72

摘要： The present invention provides a method for writing data to a non-volatile memory device having first wirings and second wirings intersecting one another and memory cells arranged at each intersection therebetween, each of the memory cells having a variable resistive element and a rectifying element connected in series. According to the method, the second wirings are charged to a certain voltage not less than a rectifying-element threshold value, prior to a rise in a selected first wiring. Then, a selected first wiring is charged to a voltage required for writing or erasing, after which a selected second wiring is discharged.

摘要翻译： 本发明提供一种将数据写入非易失性存储器件的方法，该非易失性存储器件具有彼此相交的第一布线和第二布线以及布置在其间的每个交叉处的存储单元，每个存储单元具有可变电阻元件和整流元件 系列。 根据该方法，在所选择的第一布线中升高之前，将第二布线充电至不小于整流元件阈值的一定电压。 然后，将所选择的第一布线充电到写入或擦除所需的电压，之后放电所选择的第二布线。

公开(公告)号：US07911845B2

公开(公告)日：2011-03-22

申请号：US12350398

申请日：2009-01-08

申请人： Naoya Tokiwa ,  Masanobu Shirakawa

发明人： Naoya Tokiwa ,  Masanobu Shirakawa

IPC分类号： G11C16/04

CPC分类号： G11C29/12 ,  G11C16/04 ,  G11C16/10 ,  G11C29/1201 ,  G11C2029/2602

摘要： A non-volatile semiconductor memory device includes: a memory cell array having electrically rewritable and non-volatile memory cells arranged; a data register circuit configured to hold write data to be written into the memory cell array; and an address decode circuit configured to decode a write address signal and control the write data-loading in the data register circuit, the address decode circuit being settable in such a multiple selection mode that the same write data is loaded in multiple registers in the data register circuit in correspondence to multiple addresses.

摘要翻译： 非易失性半导体存储器件包括：具有布置的电可重写和非易失性存储单元的存储单元阵列; 数据寄存器电路，被配置为保持要写入存储单元阵列的写入数据; 以及地址解码电路，被配置为对写入地址信号进行解码并且控制数据寄存器电路中的写入数据加载，地址解码电路可以以相同的写入数据被加载到数据中的多个寄存器的多重选择模式中被设置 寄存器电路对应于多个地址。

公开(公告)号：US20100238706A1

公开(公告)日：2010-09-23

申请号：US12708822

申请日：2010-02-19

申请人： Naoya TOKIWA ,  Hiroshi Maejima

发明人： Naoya TOKIWA ,  Hiroshi Maejima

IPC分类号： G11C11/00 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0085 ,  G11C2213/71 ,  G11C2213/72

摘要： A nonvolatile semiconductor storage device includes a memory core that includes plural banks, the bank including plural memory cells and a data write circuit that supplies a bias voltage to the memory cell, the memory core being logically divided into plural pages, the page including a predetermined number of memory cells belonging to a predetermined number of banks; and a control circuit that controls the data write circuit to perform page write in each write unit including a predetermined number of memory cells, pieces of data being written in the page in the page write, the control circuit performing the page write by repeating a step including a program operation and a verify operation, the control circuit performing the program operation and the verify operation in a next step or later only to the write unit in which the data write is not completed in the verify operation.

摘要翻译： 一种非易失性半导体存储装置，包括具有多个存储体的存储器芯，所述存储体包括多个存储单元，以及向所述存储单元提供偏置电压的数据写入电路，所述存储器核被逻辑地分割成多个页，所述页包括预定的 属于预定数量的存储体的存储单元的数量; 以及控制电路，其控制所述数据写入电路，在包括预定数量的存储器单元的每个写入单元中执行页写入，所述多个数据被写入所述页写入中，所述控制电路通过重复步骤 包括程序操作和验证操作，所述控制电路在下一步骤或稍后执行程序操作和验证操作仅在验证操作中仅写入数据写入的写入单元。

公开(公告)号：US07800935B2

公开(公告)日：2010-09-21

申请号：US12252675

申请日：2008-10-16

申请人： Hiroshi Maejima ,  Katsuaki Isobe ,  Naoya Tokiwa ,  Satoru Takase ,  Yasuyuki Fukuda ,  Hideo Mukai ,  Tsuneo Inaba

发明人： Hiroshi Maejima ,  Katsuaki Isobe ,  Naoya Tokiwa ,  Satoru Takase ,  Yasuyuki Fukuda ,  Hideo Mukai ,  Tsuneo Inaba

IPC分类号： G11C11/00

CPC分类号： G11C13/0009 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2211/5642 ,  G11C2213/11 ,  G11C2213/34 ,  G11C2213/56 ,  G11C2213/72

摘要： A resistance change memory device including memory cells arranged, the memory cell having a stable state with a high resistance value and storing in a non-volatile manner such multi-level data that at least three resistance values, R0, R1 and R2 (R0 ΔR2.

摘要翻译： 一种包括存储单元的电阻变化存储器件，所述存储器单元具有具有高电阻值的稳定状态并且以非易失性方式存储这样的多电平数据：至少三个电阻值R0，R1和R2（R0 < R1 ＆Dgr; R2的关系。

公开(公告)号：US20100202228A1

公开(公告)日：2010-08-12

申请号：US12767847

申请日：2010-04-27

申请人： Naoya TOKIWA

发明人： Naoya TOKIWA

IPC分类号： G11C29/04

CPC分类号： G11C16/06

摘要： A nonvolatile semiconductor storage device is disclosed, which includes a memory cell array in which nonvolatile memory cells are arranged, a first data holding circuit which temporarily holds a collective processing unit of read or write data to be simultaneously read from or written to the memory cells, a circuit which takes out the data held in the first data holding circuit from the device, and a second data holding circuit in which data is automatically set at a time when power supply is turned on and in which the data is changeable based on a command input to the device, wherein the collective processing unit is equal to a sum of the number of units used within the device and the maximum number of units continuously output from the device to outside or input to the device from outside.

摘要翻译： 公开了一种非易失性半导体存储装置，其包括其中布置非易失性存储器单元的存储单元阵列，暂时保持要同时从存储单元读取或写入存储单元的读或写数据的集合处理单元的第一数据保持电路 ，从设备取出保存在第一数据保持电路中的数据的电路，以及第二数据保持电路，其中在电源接通时自动设置数据，并且其中数据可基于 命令输入到所述设备，其中所述集体处理单元等于在所述设备内使用的单元数量与从所述设备连续输出到所述设备的外部或从外部输入到所述设备的单元的最大数量之和。

公开(公告)号：US20100188920A1

公开(公告)日：2010-07-29

申请号：US12693824

申请日：2010-01-26

申请人： Takuya FUTATSUYAMA ,  Naoya Tokiwa

发明人： Takuya FUTATSUYAMA ,  Naoya Tokiwa

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C16/30

摘要： A nonvolatile semiconductor memory device has an internal step-down power generation circuit and a memory circuit. The internal step-down power generation circuit generates a first internal power supply voltage from an external power supply voltage in an active state, and generates a second internal power supply voltage different from the first internal power supply voltage from the external power supply voltage in a standby state. The memory circuit includes a cell array containing a nonvolatile memory cell and a sense amplifier detecting data read from the cell array. The sense amplifier is supplied with a voltage generated by the internal step-down power generation circuit as an internal power supply voltage.

摘要翻译： 非易失性半导体存储器件具有内部降压发电电路和存储电路。 内部降压发电电路从活动状态的外部电源电压产生第一内部电源电压，并且从外部电源电压生成与第一内部电源电压不同的第二内部电源电压 待机状态。 存储电路包括一个包含非易失性存储单元的单元阵列和一个检测从该单元阵列读出的数据的读出放大器。 感测放大器被提供有由内部降压发电电路产生的电压作为内部电源电压。

公开(公告)号：US07724573B2

公开(公告)日：2010-05-25

申请号：US12040155

申请日：2008-02-29

申请人： Naoya Tokiwa

发明人： Naoya Tokiwa

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/06

摘要： A nonvolatile semiconductor storage device is disclosed, which includes a memory cell array in which nonvolatile memory cells are arranged, a first data holding circuit which temporarily holds a collective processing unit of read or write data to be simultaneously read from or written to the memory cells, a circuit which takes out the data held in the first data holding circuit from the device, and a second data holding circuit in which data is automatically set at a time when power supply is turned on and in which the data is changeable based on a command input to the device, wherein the collective processing unit is equal to a sum of the number of units used within the device and the maximum number of units continuously output from the device to outside or input to the device from outside.

摘要翻译： 公开了一种非易失性半导体存储装置，其包括其中布置非易失性存储器单元的存储单元阵列，暂时保持要同时从存储单元读取或写入存储单元的读或写数据的集合处理单元的第一数据保持电路 ，从设备取出保存在第一数据保持电路中的数据的电路，以及第二数据保持电路，其中在电源接通时自动设置数据，并且其中数据可基于 命令输入到所述设备，其中所述集体处理单元等于在所述设备内使用的单元数量与从所述设备连续输出到所述设备的外部或从外部输入到所述设备的单元的最大数量之和。