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公开(公告)号：US10241792B2
公开(公告)日：2019-03-26
申请号：US13993068
申请日：2011-12-30
摘要： A processor core that includes a hardware decode unit and an execution engine unit. The hardware decode unit to decode a vector frequency expand instruction, wherein the vector frequency compress instruction includes a source operand and a destination operand, wherein the source operand specifies a source vector register that includes one or more pairs of a value and run length that are to be expanded into a run of that value based on the run length. The execution engine unit to execute the decoded vector frequency expand instruction which causes, a set of one or more source data elements in the source vector register to be expanded into a set of destination data elements comprising more elements than the set of source data elements and including at least one run of identical values which were run length encoded in the source vector register.
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92.发明授权公开(公告)号：US09804844B2
公开(公告)日：2017-10-31
申请号：US13977728
申请日：2011-09-26
CPC分类号： G06F9/30043 , G06F9/30018 , G06F9/30036 , G06F9/3004 , G06F9/30101 , G06F9/3016 , G06F9/30185 , G06F9/3455 , G06F9/3808 , G06F9/3877 , G06F9/3887 , G06F15/8061
摘要： Instructions and logic provide vector load-op and/or store-op with stride functionality. Some embodiments, responsive to an instruction specifying: a set of loads, a second operation, destination register, operand register, memory address, and stride length; execution units read values in a mask register, wherein fields in the mask register correspond to stride-length multiples from the memory address to data elements in memory. A first mask value indicates the element has not been loaded from memory and a second value indicates that the element does not need to be, or has already been loaded. For each having the first value, the data element is loaded from memory into the corresponding destination register location, and the corresponding value in the mask register is changed to the second value. Then the second operation is performed using corresponding data in the destination and operand registers to generate results. The instruction may be restarted after faults.
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公开(公告)号：US20170192791A1
公开(公告)日：2017-07-06
申请号：US14984115
申请日：2015-12-30
CPC分类号： G06F9/3838 , G06F9/30 , G06F9/30021
摘要： Embodiments of systems, methods, and apparatuses for monitoring address conflicts are described. In some embodiments, an apparatus includes execution circuitry to execute instructions; a plurality of registers to store data coupled to the execution circuitry; and performance monitoring circuitry to perform address conflict counting by at least determining address conflicts between an executing instruction and previously executed instructions and counting each instance of a conflict.
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公开(公告)号：US20170192783A1
公开(公告)日：2017-07-06
申请号：US14984148
申请日：2015-12-30
IPC分类号： G06F9/30
CPC分类号： G06F9/30043 , G06F9/30036 , G06F9/3455
摘要： Embodiments of systems, apparatuses, and methods for lane-based strided load are disclosed. For example, an embodiment an apparatus includes a decoder to decode an instruction, wherein the instruction to include fields a starting source memory address operand and a packed data destination register operand; and execution circuitry to execute the decoded instruction to extract strided data elements of a defined number of types from contiguous memory beginning at the starting source memory address and, for each type, load the extracted data elements in a packed data register lane of the destination register operand dedicated to that type.
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公开(公告)号：US20170177356A1
公开(公告)日：2017-06-22
申请号：US14975612
申请日：2015-12-18
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30014 , G06F9/30018 , G06F9/30032 , G06F9/30043 , G06F9/30181 , G06F9/30192 , G06F9/3455
摘要： Systems, methods, and apparatuses for strided access are described. In some embodiments, a plurality of registers are loaded with data from an array of structures. Then data elements that that are not needed in a permute operation are overwritten with index values with a write mask. The register now contains a mix of data and index values. When this same write mask is passed to the permute instruction which overwrites the index register as destination, the data values are preserved and index values are overwritten with data coming from the other two source registers as controlled by the index values.
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公开(公告)号：US09665371B2
公开(公告)日：2017-05-30
申请号：US13977733
申请日：2011-11-30
CPC分类号： G06F9/30145 , G06F7/02 , G06F9/30018 , G06F9/30021 , G06F9/30036
摘要： Instructions and logic provide vector horizontal compare functionality. Some embodiments, responsive to an instruction specifying: a destination operand, a size of the vector elements, a source operand, and a mask corresponding to a portion of the vector element data fields in the source operand; read values from data fields of the specified size in the source operand, corresponding to the mask and compare the values for equality. In some embodiments, responsive to a detection of inequality, a trap may be taken. In some alternative embodiments, a flag may be set. In other alternative embodiments, a mask field may be set to a masked state for the corresponding unequal value(s). In some embodiments, responsive to all unmasked data fields of the source operand being equal to a particular value, that value may be broadcast to all data fields of the specified size in the destination operand.
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97.发明授权Systems, apparatuses, and methods for performing a conversion of a writemask register to a list of index values in a vector register 有权用于执行写入寄存器到矢量寄存器中的索引值的列表的系统，装置和方法公开(公告)号：US09454507B2
公开(公告)日：2016-09-27
申请号：US13992394
申请日：2011-12-23
CPC分类号： G06F9/3013 , G06F9/30018 , G06F9/30032 , G06F9/30036 , G06F9/30112 , G06F15/78
摘要： Embodiments of systems, apparatuses, and methods for performing in a computer processor conversion of a mask register into a list of index values in response to a single vector packed convert a mask register into a list of index values instruction that includes a destination vector register operand, a source writemask register operand, and an opcode are described.
摘要翻译： 用于在计算机处理器中执行的系统，装置和方法，用于响应于单个向量压缩将掩码寄存器转换为索引值列表，将掩码寄存器转换为包括目的地向量寄存器操作数的索引值指令列表 描述了源写入寄存器操作数和操作码。
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公开(公告)号：US20140317377A1
公开(公告)日：2014-10-23
申请号：US13993058
申请日：2011-12-30
申请人： Elmoustapha Ould-Ahmed-Vall , Suleyman Sair , Kshitij A. Doshi , Charles R. Yount , Bret L. Toll
发明人： Elmoustapha Ould-Ahmed-Vall , Suleyman Sair , Kshitij A. Doshi , Charles R. Yount , Bret L. Toll
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F9/30018 , G06F9/30025 , G06F9/30032 , G06F9/3016 , H03M7/46 , H03M7/6005
摘要： A processor core that includes a hardware decode unit to decode a vector frequency compress instruction that includes a source operand and a destination operand. The source operand specifying a source vector register that includes a plurality of source data elements including one or more runs of identical data elements that are each to be compressed in a destination vector register as a value and run length pair. The destination operand identifies the destination vector register. The processor core also includes an execution engine unit to execute the decoded vector frequency compress instruction which causes, for each source data element, a value to be copied into the destination vector register to indicate that source data element's value. One or more runs of the source data elements equal are encoded in the destination vector register as the predetermined compression value followed by a run length for that run.
摘要翻译： 一种处理器核心，其包括用于解码包括源操作数和目的地操作数的向量频率压缩指令的硬件解码单元。 源操作数指定源向量寄存器，其包括多个源数据元素，其包括在目的地向量寄存器中各自被压缩的相同数据元素的一个或多个游程作为值和游程长度对。 目标操作数标识目标向量寄存器。 处理器核心还包括执行引擎单元，用于执行解码的向量频率压缩指令，其对于每个源数据元素，其将被复制到目的地向量寄存器中的值指示源数据元素的值。 源数据元素相等的一个或多个运行在目标向量寄存器中被编码为预定压缩值，后跟该运行的运行长度。
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99.发明申请INSTRUCTION AND LOGIC TO PROVIDE VECTOR HORIZONTAL MAJORITY VOTING FUNCTIONALITY 有权指令和逻辑提供向量水平主要投票功能公开(公告)号：US20140289494A1
公开(公告)日：2014-09-25
申请号：US13977735
申请日：2011-11-30
IPC分类号： G06F9/30
CPC分类号： G06F9/30036 , G06F7/22 , G06F7/544 , G06F9/30018 , G06F9/30021 , G06F9/30101 , G06F9/30145 , G06F9/3016 , G06F11/1048 , G06F11/1479
摘要： Instructions and logic provide vector horizontal majority voting functionality. Some embodiments, responsive to an instruction specifying: a destination operand, a size of the vector elements, a source operand, and a mask corresponding to a portion of the vector element data fields in the source operand; read a number of values from data fields of the specified size in the source operand, corresponding to the mask specified by the instruction and store a result value to that number of corresponding data fields in the destination operand, the result value computed from the majority of values read from the number of data fields of the source operand.
摘要翻译： 指令和逻辑提供向量横向多数投票功能。 一些实施例，响应于指定目的地操作数，向量元素的大小，源操作数和对应于源操作数中的向量元素数据字段的一部分的掩码的指令; 从源操作数中的指定大小的数据字段读取一些数值，对应于指令指定的掩码，并将结果值存储到目标操作数中的相应数据字段数，从大多数 从源操作数的数据字段数读取的值。
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100.发明申请公开(公告)号：US20140258683A1
公开(公告)日：2014-09-11
申请号：US13977733
申请日：2011-11-30
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F7/02 , G06F9/30018 , G06F9/30021 , G06F9/30036
摘要： Instructions and logic provide vector horizontal compare functionality. Some embodiments, responsive to an instruction specifying: a destination operand, a size of the vector elements, a source operand, and a mask corresponding to a portion of the vector element data fields in the source operand; read values from data fields of the specified size in the source operand, corresponding to the mask and compare the values for equality. In some embodiments, responsive to a detection of inequality, a trap may be taken. In some alternative embodiments, a flag may be set. In other alternative embodiments, a mask field may be set to a masked state for the corresponding unequal value(s). In some embodiments, responsive to all unmasked data fields of the source operand being equal to a particular value, that value may be broadcast to all data fields of the specified size in the destination operand.
摘要翻译： 指令和逻辑提供向量横向比较功能。 一些实施例，响应于指定目的地操作数，向量元素的大小，源操作数和对应于源操作数中的向量元素数据字段的一部分的掩码的指令; 从源操作数中的指定大小的数据字段读取值，对应于掩码，并比较相等的值。 在一些实施例中，响应于不等式的检测，可以采取陷阱。 在一些替代实施例中，可以设置标志。 在其他替代实施例中，可以将掩模字段设置为对应不等值的掩蔽状态。 在一些实施例中，响应于源操作数的所有未屏蔽的数据字段等于特定值，该值可以广播到目的地操作数中指定大小的所有数据字段。
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