公开(公告)号：US20100026351A1

公开(公告)日：2010-02-04

申请号：US12574847

申请日：2009-10-07

Applicant: Feng Lin

Inventor： Feng Lin

IPC: H03L7/00

CPC classification number: G11C7/222 ,  G06F1/10 ,  G11C7/22 ,  H03L7/0814

Abstract: A phase detection system for use with a synchronous mirror delay or a delay-locked loop in order to reduce the number of delay stages required, and therefore increase the efficiency, is disclosed. The invention includes taking a clock input signal and a clock delay or feedback signal, each having timing characteristics, and differentiating between four conditions based upon the timing characteristics of the signals. The phase detector and associated circuitry then determines, based upon the timing characteristics of the signals, which of a number of phase conditions the signals are in. Selectors select the signals to be introduced into the synchronous mirror delay or delay-locked loop by the timing characteristics of the phase conditions. The system is able to utilize the falling clock edge of the clock input signal, and the lock time is decreased under specific phase conditions. The invention increases the efficiency of the circuits by reducing the effective delay stages in the SMD or DLL while maintaining the operating range.

Abstract translation: 公开了一种用于同步镜延迟或延迟锁定环路的相位检测系统，以便减少所需的延迟级数，从而提高效率。 本发明包括采用每个具有定时特性的时钟输入信号和时钟延迟或反馈信号，并且基于信号的定时特性来区分四个条件。 相位检测器和相关电路然后基于信号的定时特性来确定信号处于多个相位条件中的哪一个。选择器通过定时选择要被引入同步镜延迟或延迟锁定环路的信号 相位条件的特征。 该系统能够利用时钟输入信号的下降时钟边沿，并且在特定相位条件下锁定时间减少。 本发明通过在保持工作范围的同时减少SMD或DLL中的有效延迟级来提高电路的效率。

公开(公告)号：US07639090B2

公开(公告)日：2009-12-29

申请号：US12324077

申请日：2008-11-26

Applicant: Feng Lin

Inventor： Feng Lin

IPC: H03L7/06

CPC classification number: H03L7/0814 ,  H03L7/07 ,  H03L7/089

Abstract: The present invention provides a method and an apparatus for reducing noise. The apparatus includes a phase detector adapted to determine a phase difference between a first and a second signal, a first circuit adapted to generate a control signal based upon the determined phase difference, and a second circuit. The second circuit is adapted to receive a third signal, receive a fourth signal, modify the fourth signal based upon the control signal, and provide the third signal and the modified fourth signal to the phase detector as the first and second signals.

Abstract translation: 本发明提供一种降低噪声的方法和装置。 该装置包括相位检测器，其适于确定第一和第二信号之间的相位差，适于基于所确定的相位差产生控制信号的第一电路和第二电路。 第二电路适于接收第三信号，接收第四信号，基于控制信号修改第四信号，并将第三信号和修改的第四信号提供给相位检测器作为第一和第二信号。

公开(公告)号：US07619458B2

公开(公告)日：2009-11-17

申请号：US11521837

申请日：2006-09-14

Applicant: Feng Lin

Inventor： Feng Lin

IPC: H03K3/00

CPC classification number: G11C29/02 ,  G11C7/20 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4072 ,  G11C11/4076 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012 ,  G11C2029/0409

Abstract: A delay-lock loop receives an input clock signal from the output of a programmable divider that receives a reference clock signal. The delay-lock loop includes a voltage-controlled delay line generating a plurality of delayed clock signals having different phases. A plurality of the delayed clock signals are combined to generate a plurality of output signals. During an initialization period, an initialization circuit sets the delay of the delay line to a minimum delay value and then compares this delay value to the period of the input clock signal. Based on this comparison, the initialization circuit programs the programmable divider and adjusts the number of delayed clock signals combined to generate the output signals. More specifically, as the frequency of the reference clock signal increases, the divider is programmed to divide by a greater number, and a larger number of delay clock signals are combined to generate the output signals.

Abstract translation: 延迟锁定环路接收来自接收参考时钟信号的可编程分频器的输出端的输入时钟信号。 延迟锁定环包括产生具有不同相位的多个延迟时钟信号的电压控制延迟线。 多个延迟的时钟信号被组合以产生多个输出信号。 在初始化期间，初始化电路将延迟线的延迟设定为最小延迟值，然后将该延迟值与输入时钟信号的周期进行比较。 基于该比较，初始化电路对可编程分频器进行编程，并调整组合的延迟时钟信号的数量以产生输出信号。 更具体地，随着参考时钟信号的频率增加，分频器被编程为除以更大的数量，并且更大数量的延迟时钟信号被组合以产生输出信号。

公开(公告)号：US20090258039A1

公开(公告)日：2009-10-15

申请号：US12370117

申请日：2009-02-12

Applicant: Frank J. Bunick ,  Feng Lin

Inventor： Frank J. Bunick ,  Feng Lin

IPC: A61K47/30 ,  A61K31/167 ,  A61K31/192 ,  A61K31/137 ,  A61K31/426 ,  A61K9/00 ,  A61K47/32 ,  A61K47/38 ,  A61K47/42

CPC classification number: A61K9/2072 ,  A61K9/0056 ,  A61K9/286 ,  A61K9/2866

Abstract: A method for reducing the friability of soft substrates by applying an effective amount of a water soluble, polymeric dispersion to at least a portion of a treatment surface of the substrate, such that less than about 90% of the exterior surface has the dispersion applied thereto.

Abstract translation: 一种通过将有效量的水溶性聚合物分散体施加到基材的处理表面的至少一部分来降低软基材的脆性的方法，使得少于约90％的外表面具有施加到其上的分散体 。

公开(公告)号：US20090240970A1

公开(公告)日：2009-09-24

申请号：US12051745

申请日：2008-03-19

Applicant: Feng Lin

Inventor： Feng Lin

IPC: G06F1/04

CPC classification number: G06F1/10 ,  G06F1/3203 ,  G06F1/3237 ,  Y02D10/128

Abstract: Apparatus, systems, and methods are disclosed that operate to adjust power received by a clock distribution network at least partially based on operating conditions of an integrated circuit. Additional apparatus, systems, and methods are disclosed.

Abstract translation: 公开了用于至少部分地基于集成电路的操作条件来调整由时钟分配网络接收的功率的装置，系统和方法。 公开了附加装置，系统和方法。

公开(公告)号：US07463099B2

公开(公告)日：2008-12-09

申请号：US11524842

申请日：2006-09-21

Applicant: Feng Lin

Inventor： Feng Lin

IPC: H03D3/00

CPC classification number: H03L7/0814 ,  H03L7/07 ,  H03L7/089

Abstract: The present invention provides a method and an apparatus for reducing noise. The apparatus includes a phase detector adapted to determine a phase difference between a first and a second signal, a first circuit adapted to generate a control signal based upon the determined phase difference, and a second circuit. The second circuit is adapted to receive a third signal, receive a fourth signal, modify the fourth signal based upon the control signal, and provide the third signal and the modified fourth signal to the phase detector as the first and second signals.

Abstract translation: 本发明提供一种降低噪声的方法和装置。 该装置包括相位检测器，其适于确定第一和第二信号之间的相位差，适于基于所确定的相位差产生控制信号的第一电路和第二电路。 第二电路适于接收第三信号，接收第四信号，基于控制信号修改第四信号，并将第三信号和修改的第四信号提供给相位检测器作为第一和第二信号。

公开(公告)号：US07449939B2

公开(公告)日：2008-11-11

申请号：US11895419

申请日：2007-08-24

Applicant: Feng Lin

Inventor： Feng Lin

IPC: G05F1/10

CPC classification number: H03L7/10 ,  G11C7/20 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812

Abstract: A bias generator for initializing a voltage controlled delay line by providing the voltage controlled delay line with a control signal having an initial voltage and monitoring the variable delay line for an output clock signal. The voltage of the control signal is varied from the initial voltage until an output clock signal from the voltage controlled delay line is detected by the bias generator.

Abstract translation: 一种偏置发生器，用于通过向电压控制的延迟线提供具有初始电压的控制信号并监视输出时钟信号的可变延迟线来初始化电压控制延迟线。 控制信号的电压从初始电压变化，直到来自电压控制的延迟线的输出时钟信号被偏置发生器检测到。

公开(公告)号：US07443761B2

公开(公告)日：2008-10-28

申请号：US11358266

申请日：2006-02-21

Applicant: Feng Lin

Inventor： Feng Lin

IPC: G11C8/00

CPC classification number: H03L7/081 ,  G11C7/22 ,  G11C7/222 ,  H03L7/0812 ,  H03L7/0891 ,  H03L7/093 ,  H03L7/107 ,  H03L7/1075

Abstract: Methods, circuits, devices, and systems are provided for phase locked loop (PLL) locking. A method of locking a PLL includes locking a delay locked loop (DLL) path while applying a control voltage of the DLL path to a loop filter of the DLL path. The method includes locking a DLL voltage while applying the control voltage of the DLL path to the loop filter of the DLL path. The method also includes transferring the control voltage from the loop filter of the DLL path to a loop filter of the PLL path after the DLL voltage locks.

Abstract translation: 提供了锁相环（PLL）锁定的方法，电路，器件和系统。 锁定PLL的方法包括锁定延迟锁定环（DLL）路径，同时将DLL路径的控制电压施加到DLL路径的环路滤波器。 该方法包括锁定DLL电压，同时将DLL路径的控制电压施加到DLL路径的环路滤波器。 该方法还包括在DLL电压锁定之后将控制电压从DLL路径的环路滤波器传送到PLL路径的环路滤波器。

公开(公告)号：US07443743B2

公开(公告)日：2008-10-28

申请号：US11837631

申请日：2007-08-13

Applicant: Feng Lin

Inventor： Feng Lin

IPC: G11C7/00 ,  G11C8/00 ,  G11C8/18 ,  H03L7/00 ,  H03L7/06

CPC classification number: G11C7/22 ,  G11C7/222 ,  G11C11/4076

Abstract: A plurality of improved memory systems employing a phase detection system in conjunction with either a synchronous mirror delay or a delay-locked loop, and related methods of operation, are disclosed. The memory systems determine timing characteristics among multiple signals and, based upon those timing characteristics, vary which clock-related signal is output. The improvement relates in part to the incorporation of a clock divider that reduces the frequency of the clock signals utilized by the system. Due to the incorporation of the clock divider and an edge recovery device, attenuation, power dissipation and duty cycle distortion associated with propagation of the clock signal(s) are reduced. Further, the reduction in frequency of the clock signals allows for numerous differently-phased clock signals to be generated within the system, which allows for finer timing comparisons to be performed, thus allowing for finer selections to be made in relation to which clock-related signal is output.

Abstract translation: 公开了采用与同步镜像延迟或延迟锁定环路相结合的相位检测系统和相关操作方法的多个改进的存储器系统。 存储器系统确定多个信号之间的定时特性，并且基于这些定时特性，改变哪个时钟相关信号被输出。 该改进部分地涉及并入一个降低系统所使用的时钟信号频率的时钟分频器。 由于并入时钟分频器和边沿恢复装置，与时钟信号的传播相关联的衰减，功耗和占空比失真减少。 此外，时钟信号的频率的降低允许在系统内产生许多不同阶段的时钟信号，这允许执行更精细的时序比较，从而允许对哪个时钟相关的更精细的选择 信号输出。

公开(公告)号：US07420361B2

公开(公告)日：2008-09-02

申请号：US11519556

申请日：2006-09-12

Applicant: Feng Lin ,  J. Brian Johnson

Inventor： Feng Lin ,  J. Brian Johnson

IPC: G01R13/02

CPC classification number: G11C29/12015 ,  G11C7/02 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/028 ,  G11C29/50012

Abstract: Delay-locked loops, signal locking methods and devices and systems incorporating delay-locked loops are described. A delay-locked loop includes a forward delay path, a feedback delay path, a phase detector and a timer circuit. The forward delay path alternatively couples to an external clock signal and to an internal test signal. The phase detector adjusts a delay line based upon the phase differences of a feedback signal and the external clock signal. The timer circuit switches the internal test signal into the forward delay path and measures the time of traversal of the internal test signal around the forward delay path and the feedback delay path and generates a time constant for configuring the phase detector's update period. The phase detector is thereafter able to stabilize at an improved rate.

Abstract translation: 描述了延迟锁定环路，信号锁定方法以及包含延迟锁定环路的设备和系统。 延迟锁定环包括正向延迟路径，反馈延迟路径，相位检测器和定时器电路。 前向延迟路径交替耦合到外部时钟信号和内部测试信号。 相位检测器根据反馈信号和外部时钟信号的相位差调整延迟线。 定时器电路将内部测试信号切换到正向延迟路径，并测量在正向延迟路径和反馈延迟路径周围的内部测试信号的遍历时间，并产生用于配置相位检测器更新周期的时间常数。 此后，相位检测器能够以更高的速率稳定。