公开(公告)号：US20120014168A1

公开(公告)日：2012-01-19

申请号：US13243814

申请日：2011-09-23

申请人： Hai Li ,  Yiran Chen ,  Yuan Yan ,  Brian Lee ,  Ran Wang

发明人： Hai Li ,  Yiran Chen ,  Yuan Yan ,  Brian Lee ,  Ran Wang

IPC分类号： G11C11/00 ,  G11C7/06

CPC分类号： G11C7/02 ,  G11C7/06 ,  G11C11/1673 ,  G11C11/1693

摘要： A method and apparatus for accessing a non-volatile memory cell. In some embodiments, a memory block provides a plurality of memory cells arranged into rows and columns. A read circuit is configured to read a selected row of the memory block by concurrently applying a control voltage to each memory cell along the selected row and, for each column, using a respective local sense amplifier and a column sense amplifier to successively differentiate a voltage across the associated memory cell in said column to output a programmed content of the row.

摘要翻译： 一种用于访问非易失性存储单元的方法和装置。 在一些实施例中，存储块提供布置成行和列的多个存储器单元。 读取电路被配置为通过同时向沿着所选行的每个存储器单元施加控制电压并且对于每列使用相应的本地读出放大器和列读出放大器来连续地区分电压来读取存储器块的选定行 在所述列中的相关联的存储器单元之间输出该行的编程内容。

公开(公告)号：US08098510B2

公开(公告)日：2012-01-17

申请号：US12944790

申请日：2010-11-12

申请人： Maroun Georges Khoury ,  Hongyue Liu ,  Brian Lee ,  Andrew John Gjevre Carter

发明人： Maroun Georges Khoury ,  Hongyue Liu ,  Brian Lee ,  Andrew John Gjevre Carter

IPC分类号： G11C11/00

CPC分类号： G11C11/1675 ,  G11C11/1659

摘要： Variable resistive punchthrough access methods are described. The methods include switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction. The write current is provided by a transistor being electrically coupled to the variable resistive data cell and a source line. The write current passes through the transistor in punchthrough mode.

摘要翻译： 描述了可变电阻穿透访问方法。 所述方法包括通过使写入电流沿着第一方向通过磁性隧道结数据单元，将可变电阻数据单元从高电阻状态切换到低电阻状态。 写入电流由电耦合到可变电阻数据单元和源极线的晶体管提供。 写入电流在穿通模式下通过晶体管。

公开(公告)号：US20110156115A1

公开(公告)日：2011-06-30

申请号：US13042508

申请日：2011-03-08

申请人： Maroun Georges Khoury ,  Hongyue Liu ,  Brian Lee ,  Andrew John Gjevre Carter

发明人： Maroun Georges Khoury ,  Hongyue Liu ,  Brian Lee ,  Andrew John Gjevre Carter

IPC分类号： H01L29/02

CPC分类号： G11C11/1675 ,  G11C11/1659

摘要： Variable resistive punchthrough access methods are described. The methods include switching a variable resistive data cell from a high resistance state to a low resistance state by passing a write current through the magnetic tunnel junction data cell in a first direction. The write current is provided by a transistor being electrically coupled to the variable resistive data cell and a source line. The write current passes through the transistor in punchthrough mode.

摘要翻译： 描述了可变电阻穿透访问方法。 所述方法包括通过使写入电流沿着第一方向通过磁性隧道结数据单元，将可变电阻数据单元从高电阻状态切换到低电阻状态。 写入电流由电耦合到可变电阻数据单元和源极线的晶体管提供。 写入电流在穿通模式下通过晶体管。

公开(公告)号：US07936622B2

公开(公告)日：2011-05-03

申请号：US12502194

申请日：2009-07-13

申请人： Hai Li ,  Yiran Chen ,  Dadi Setiadi ,  Harry Hongyue Liu ,  Brian Lee

发明人： Hai Li ,  Yiran Chen ,  Dadi Setiadi ,  Harry Hongyue Liu ,  Brian Lee

IPC分类号： G11C29/00

CPC分类号： G11C5/04 ,  G11C5/02 ,  G11C5/025 ,  G11C29/44 ,  G11C29/808 ,  G11C2029/0403

摘要： Various embodiments of the present invention are generally directed to an apparatus and associated method for handling defective bits in a multi-layer integrated memory device. In accordance with some embodiments, the multi-layer integrated memory device is formed from a plurality of vertically stacked semiconductor layers each having a number of storage sub-arrays and redundant sub-arrays. Each semiconductor layer is tested to determine a defect rate for each array, and a defective portion of a first semiconductor layer having a relatively higher defect rate is stored to a redundant sub-array of a second semiconductor layer having a relatively lower defect rate.

摘要翻译： 本发明的各种实施例一般涉及用于处理多层集成存储器件中的不良位的装置和相关方法。 根据一些实施例，多层集成存储器件由多个垂直堆叠的半导体层形成，每个半导体层具有多个存储子阵列和冗余子阵列。 测试每个半导体层以确定每个阵列的缺陷率，并且将具有相对较高缺陷率的第一半导体层的缺陷部分存储到具有相对较低缺陷率的第二半导体层的冗余子阵列中。

公开(公告)号：US20110000755A1

公开(公告)日：2011-01-06

申请号：US12818751

申请日：2010-06-18

申请人： Tomas Smetana ,  Brian Lee

发明人： Tomas Smetana ,  Brian Lee

IPC分类号： F16D41/066

CPC分类号： F16D41/088 ,  F16D15/00

摘要： A coupling having at least two concentric rings, each having a circumferential surface and a recess, and at least two roller elements. The roller elements are each disposed in a channel formed by the circumferential surface of one of the rings and the recess of another of the rings. In some example embodiments of the invention, the coupling includes a coupling member with a bearing surface, at least one of the rings includes a split and the split ring is urged against the bearing surface when there is relative rotation between the rings. The coupling member is, for example, a shaft or a gear.

摘要翻译： 具有至少两个同心环的联接器，每个具有圆周表面和凹槽，以及至少两个滚子元件。 辊元件各自设置在由一个环的圆周表面和另一个环的凹部形成的通道中。 在本发明的一些示例性实施例中，联接器包括具有支承表面的联接构件，至少一个环包括开口，并且当环之间存在相对旋转时，开口环被推靠在支承表面上。 联接构件例如是轴或齿轮。

公开(公告)号：US20100302849A1

公开(公告)日：2010-12-02

申请号：US12474463

申请日：2009-05-29

申请人： Chulmin Jung ,  Harry Hongyue Liu ,  Brian Lee ,  Yong Lu ,  Dadi Setiadi

发明人： Chulmin Jung ,  Harry Hongyue Liu ,  Brian Lee ,  Yong Lu ,  Dadi Setiadi

IPC分类号： G11C14/00 ,  G11C16/04

CPC分类号： G11C11/005 ,  G11C16/26 ,  G11C2216/14

摘要： Method and apparatus for outputting data from a memory array having a plurality of non-volatile memory cells arranged into rows and columns. In accordance with various embodiments, charge is stored in a volatile memory cell connected to the memory array, and the stored charge is subsequently discharged from the volatile memory cell through a selected column. In some embodiments, the volatile memory cell is a dynamic random access memory (DRAM) cell from a row of said cells with each DRAM cell along the row coupled to a respective column in the memory array, and each column of non-volatile memory cells comprises Flash memory cells connected in a NAND configuration.

摘要翻译： 用于从具有排列成行和列的多个非易失性存储单元的存储器阵列输出数据的方法和装置。 根据各种实施例，电荷被存储在连接到存储器阵列的易失性存储单元中，并且随后通过所选择的列从易失性存储器单元中释放存储的电荷。 在一些实施例中，易失性存储器单元是来自所述单元的行的动态随机存取存储器（DRAM）单元，其中每个DRAM单元沿着与存储器阵列中的相应列耦合的行，并且每列非易失性存储单元 包括以NAND配置连接的闪存单元。

公开(公告)号：US20100126817A1

公开(公告)日：2010-05-27

申请号：US12604133

申请日：2009-10-22

申请人： TOMAS SMETANA ,  Brian Lee

发明人： TOMAS SMETANA ,  Brian Lee

IPC分类号： F16D13/04

CPC分类号： F16D41/20 ,  F16D41/06

摘要： Example aspects of the present invention broadly comprise at least two concentric rings with complementary ramped surfaces, at least one of the rings being rotatable relative to another one of the rings so that contact is made at the ramped surfaces. The complementary ramped surfaces form respective circumferences of the rings. At least one of the ramped surfaces may have a sinusoidal profile, or a profile forming at least one of a straight line, concave, or convex. In some example embodiments of the invention, a first one of the rings is a coupling member and a second one of the rings is a tubular slipper with a friction surface radially opposite of the ramped surface. The tubular slipper is arranged to radially expand or contract upon contacting the coupling member.

摘要翻译： 本发明的示例性方面广泛地包括具有互补倾斜表面的至少两个同心环，至少一个环可以相对于另一个环可旋转，使得在斜面处形成接触。 互补的倾斜表面形成环的相应周长。 倾斜表面中的至少一个可以具有正弦曲线或形成直线，凹入或凸起中的至少一个的轮廓。 在本发明的一些示例实施例中，第一环是联接构件，并且第二环是具有径向相对于倾斜表面的摩擦表面的管状拖鞋。 管状拖鞋布置成在联接构件接触时径向膨胀或收缩。

公开(公告)号：US20100085797A1

公开(公告)日：2010-04-08

申请号：US12490493

申请日：2009-06-24

申请人： Hai Li ,  Yiran Chen ,  Yuan Yan ,  Brian Lee ,  Ran Wang

发明人： Hai Li ,  Yiran Chen ,  Yuan Yan ,  Brian Lee ,  Ran Wang

IPC分类号： G11C11/00 ,  G11C7/02 ,  G11C7/00

CPC分类号： G11C7/02 ,  G11C7/06 ,  G11C11/1673 ,  G11C11/1693

摘要： A method and apparatus for accessing a non-volatile memory cell. In some embodiments, a memory block provides a plurality of memory cells arranged into rows and columns. A read circuit is configured to read a selected row of the memory block by concurrently applying a control voltage to each memory cell along the selected row and, for each column, using a respective local sense amplifier and a column sense amplifier to successively differentiate a voltage across the associated memory cell in said column to output a programmed content of the row.

摘要翻译： 一种用于访问非易失性存储单元的方法和装置。 在一些实施例中，存储块提供布置成行和列的多个存储器单元。 读取电路被配置为通过同时向沿着所选行的每个存储器单元施加控制电压并且对于每列使用相应的本地读出放大器和列读出放大器来连续地区分电压来读取存储器块的选定行 在所述列中的相关联的存储器单元之间输出该行的编程内容。

公开(公告)号：US20100037020A1

公开(公告)日：2010-02-11

申请号：US12200118

申请日：2008-08-28

申请人： Hai Li ,  Yiran Chen ,  Hongyue Liu ,  Dadi Setiadi ,  Brian Lee

发明人： Hai Li ,  Yiran Chen ,  Hongyue Liu ,  Dadi Setiadi ,  Brian Lee

IPC分类号： G06F12/00

CPC分类号： G11C7/1039 ,  G11C8/10 ,  G11C8/18

摘要： A memory array and a method for accessing a memory array including: receiving an address from a host related to relevant data; accessing a first module based on the address received from the host, wherein accessing the first module includes: decoding the address for the first module; enabling a wordline based on the decoded address for the first module and sensing the contents of one or more bits at the decoded address for the first module; and outputting information regarding the first module; and accessing a second module based on the address received from the host, wherein accessing the second module includes: decoding the address for the second module; enabling a wordline based on the decoded address for the second module and sensing the contents of one or more bits at the decoded address for the second module; and outputting information regarding the second module, wherein the step of decoding the address for the second module occurs while the step of enabling a wordline based on the decoded address for the first module and sensing the contents of one or more bits at the decoded address for the first module occurs.

摘要翻译： 一种用于访问存储器阵列的存储器阵列和方法，包括：从相关数据相关的主机接收地址; 基于从所述主机接收的地址访问第一模块，其中访问所述第一模块包括：解码所述第一模块的地址; 基于第一模块的解码地址启用字线，并感测第一模块的解码地址处的一个或多个位的内容; 并输出关于第一模块的信息; 以及基于从所述主机接收的地址访问第二模块，其中访问所述第二模块包括：对所述第二模块的地址进行解码; 基于第二模块的解码地址启用字线，并感测第二模块的解码地址处的一个或多个位的内容; 以及输出关于第二模块的信息，其中对第二模块的地址进行解码的步骤在基于第一模块的解码地址启用字线的步骤并且感测解码地址处的一个或多个位的内容的步骤 第一个模块发生。

公开(公告)号：US07394639B2

公开(公告)日：2008-07-01

申请号：US11177814

申请日：2005-07-08

申请人： Kenneth Finley ,  Michael J. Zolock ,  Brian Lee

发明人： Kenneth Finley ,  Michael J. Zolock ,  Brian Lee

IPC分类号： H01H57/00 ,  H02N2/00

CPC分类号： H02N2/062

摘要： A process control apparatus including an actuator configured to effect changes in an industrial process, a power supply, a plurality of current switches coupled between the actuator and the power supply and a controller coupled to the plurality of current switches. The controller is configured to selectively close one or more of the plurality of current switches so as to provide a selectable level of current from the power supply to the actuator. In variations, a plurality of discharge switches are coupled to the actuator and the controller is configured to selectively close the discharge switches so as to provide a selectable level of charge to discharge from the actuator.

摘要翻译： 一种过程控制装置，包括致动器，其被配置为实现工业过程，电源，耦合在致动器和电源之间的多个电流开关以及耦合到多个电流开关的控制器的变化。 控制器被配置为选择性地关闭多个电流开关中的一个或多个，以便从电源向致动器提供可选择的电流水平。 在变型中，多个放电开关耦合到致动器，并且控制器被配置为选择性地关闭放电开关，以便提供可选择的电荷水平以从致动器排出。