公开(公告)号：US20110007588A1

公开(公告)日：2011-01-13

申请号：US12502194

申请日：2009-07-13

申请人： Hai Li ,  Yiran Chen ,  Dadi Setiadi ,  Harry Hongyue Liu ,  Brian Lee

发明人： Hai Li ,  Yiran Chen ,  Dadi Setiadi ,  Harry Hongyue Liu ,  Brian Lee

IPC分类号： G11C29/00 ,  G11C29/04 ,  G11C15/00

CPC分类号： G11C5/04 ,  G11C5/02 ,  G11C5/025 ,  G11C29/44 ,  G11C29/808 ,  G11C2029/0403

摘要： Various embodiments of the present invention are generally directed to an apparatus and associated method for handling defective bits in a multi-layer integrated memory device. In accordance with some embodiments, the multi-layer integrated memory device is formed from a plurality of vertically stacked semiconductor layers each having a number of storage sub-arrays and redundant sub-arrays. Each semiconductor layer is tested to determine a defect rate for each array, and a defective portion of a first semiconductor layer having a relatively higher defect rate is stored to a redundant sub-array of a second semiconductor layer having a relatively lower defect rate.

摘要翻译： 本发明的各种实施例一般涉及用于处理多层集成存储器件中的不良位的装置和相关方法。 根据一些实施例，多层集成存储器件由多个垂直堆叠的半导体层形成，每个半导体层具有多个存储子阵列和冗余子阵列。 测试每个半导体层以确定每个阵列的缺陷率，并且将具有相对较高缺陷率的第一半导体层的缺陷部分存储到具有相对较低缺陷率的第二半导体层的冗余子阵列中。

公开(公告)号：US07936622B2

公开(公告)日：2011-05-03

申请号：US12502194

申请日：2009-07-13

申请人： Hai Li ,  Yiran Chen ,  Dadi Setiadi ,  Harry Hongyue Liu ,  Brian Lee

发明人： Hai Li ,  Yiran Chen ,  Dadi Setiadi ,  Harry Hongyue Liu ,  Brian Lee

IPC分类号： G11C29/00

CPC分类号： G11C5/04 ,  G11C5/02 ,  G11C5/025 ,  G11C29/44 ,  G11C29/808 ,  G11C2029/0403

摘要： Various embodiments of the present invention are generally directed to an apparatus and associated method for handling defective bits in a multi-layer integrated memory device. In accordance with some embodiments, the multi-layer integrated memory device is formed from a plurality of vertically stacked semiconductor layers each having a number of storage sub-arrays and redundant sub-arrays. Each semiconductor layer is tested to determine a defect rate for each array, and a defective portion of a first semiconductor layer having a relatively higher defect rate is stored to a redundant sub-array of a second semiconductor layer having a relatively lower defect rate.

摘要翻译： 本发明的各种实施例一般涉及用于处理多层集成存储器件中的不良位的装置和相关方法。 根据一些实施例，多层集成存储器件由多个垂直堆叠的半导体层形成，每个半导体层具有多个存储子阵列和冗余子阵列。 测试每个半导体层以确定每个阵列的缺陷率，并且将具有相对较高缺陷率的第一半导体层的缺陷部分存储到具有相对较低缺陷率的第二半导体层的冗余子阵列中。

公开(公告)号：US20100037020A1

公开(公告)日：2010-02-11

申请号：US12200118

申请日：2008-08-28

申请人： Hai Li ,  Yiran Chen ,  Hongyue Liu ,  Dadi Setiadi ,  Brian Lee

发明人： Hai Li ,  Yiran Chen ,  Hongyue Liu ,  Dadi Setiadi ,  Brian Lee

IPC分类号： G06F12/00

CPC分类号： G11C7/1039 ,  G11C8/10 ,  G11C8/18

摘要： A memory array and a method for accessing a memory array including: receiving an address from a host related to relevant data; accessing a first module based on the address received from the host, wherein accessing the first module includes: decoding the address for the first module; enabling a wordline based on the decoded address for the first module and sensing the contents of one or more bits at the decoded address for the first module; and outputting information regarding the first module; and accessing a second module based on the address received from the host, wherein accessing the second module includes: decoding the address for the second module; enabling a wordline based on the decoded address for the second module and sensing the contents of one or more bits at the decoded address for the second module; and outputting information regarding the second module, wherein the step of decoding the address for the second module occurs while the step of enabling a wordline based on the decoded address for the first module and sensing the contents of one or more bits at the decoded address for the first module occurs.

摘要翻译： 一种用于访问存储器阵列的存储器阵列和方法，包括：从相关数据相关的主机接收地址; 基于从所述主机接收的地址访问第一模块，其中访问所述第一模块包括：解码所述第一模块的地址; 基于第一模块的解码地址启用字线，并感测第一模块的解码地址处的一个或多个位的内容; 并输出关于第一模块的信息; 以及基于从所述主机接收的地址访问第二模块，其中访问所述第二模块包括：对所述第二模块的地址进行解码; 基于第二模块的解码地址启用字线，并感测第二模块的解码地址处的一个或多个位的内容; 以及输出关于第二模块的信息，其中对第二模块的地址进行解码的步骤在基于第一模块的解码地址启用字线的步骤并且感测解码地址处的一个或多个位的内容的步骤 第一个模块发生。

公开(公告)号：US20100100857A1

公开(公告)日：2010-04-22

申请号：US12252564

申请日：2008-10-16

申请人： Yiran Chen ,  Dadi Setiadi ,  Hai Li ,  Haiwen Xi ,  Hongyue Liu

发明人： Yiran Chen ,  Dadi Setiadi ,  Hai Li ,  Haiwen Xi ,  Hongyue Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/14

摘要： Method and apparatus for constructing and operating an integrated circuit in an electronic device. In some embodiments, a generic service layer is integrated in a three dimensional integrated circuit and tested using a testing pattern stored in a non-volatile memory. The generic service layer is reconfigured to a permanent non-testing functional component of the integrated circuit.

摘要翻译： 在电子设备中构建和操作集成电路的方法和装置。 在一些实施例中，通用服务层集成在三维集成电路中，并使用存储在非易失性存储器中的测试模式进行测试。 通用服务层被重新配置为集成电路的永久性非测试功能组件。

公开(公告)号：US07966581B2

公开(公告)日：2011-06-21

申请号：US12252564

申请日：2008-10-16

申请人： Yiran Chen ,  Dadi Setiadi ,  Hai Li ,  Haiwen Xi ,  Hongyue Liu

发明人： Yiran Chen ,  Dadi Setiadi ,  Hai Li ,  Haiwen Xi ,  Hongyue Liu

IPC分类号： G06F17/50

CPC分类号： G06F17/5045 ,  G06F2217/14

摘要： Method and apparatus for constructing and operating an integrated circuit in an electronic device. In some embodiments, a generic service layer is integrated in a three dimensional integrated circuit and tested using a testing pattern stored in a non-volatile memory. The generic service layer is reconfigured to a permanent non-testing functional component of the integrated circuit.

摘要翻译： 在电子设备中构建和操作集成电路的方法和装置。 在一些实施例中，通用服务层集成在三维集成电路中，并使用存储在非易失性存储器中的测试模式进行测试。 通用服务层被重新配置为集成电路的永久性非测试功能组件。

公开(公告)号：US08009457B2

公开(公告)日：2011-08-30

申请号：US12967802

申请日：2010-12-14

申请人： Hai Li ,  Yiran Chen ,  Harry Hongyue Liu ,  Henry Huang ,  Ran Wang

发明人： Hai Li ,  Yiran Chen ,  Harry Hongyue Liu ,  Henry Huang ,  Ran Wang

IPC分类号： G11C11/00 ,  G11C17/00 ,  G11C5/14 ,  G11C8/00

CPC分类号： G11C8/08 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2013/0071

摘要： Apparatus and method for write current compensation in a non-volatile memory cell, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM). In accordance with some embodiments, a non-volatile memory cell has a resistive sense element (RSE) coupled to a switching device, the RSE having a hard programming direction and an easy programming direction opposite the hard programming direction. A voltage boosting circuit includes a capacitor which adds charge to a nominal non-zero voltage supplied by a voltage source to a node to generate a temporarily boosted voltage. The boosted voltage is applied to the switching device when the RSE is programmed in the hard programming direction.

公开(公告)号：US07974121B2

公开(公告)日：2011-07-05

申请号：US12967743

申请日：2010-12-14

申请人： Hai Li ,  Yiran Chen ,  Harry Hongyue Liu ,  Henry Huang ,  Ran Wang

发明人： Hai Li ,  Yiran Chen ,  Harry Hongyue Liu ,  Henry Huang ,  Ran Wang

IPC分类号： G11C11/00 ,  G11C11/14 ,  G11C5/14 ,  G11C8/00

CPC分类号： G11C8/08 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2013/0071

摘要： Apparatus and method for write current compensation in a non-volatile memory cell, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM). In accordance with some embodiments, a non-volatile memory cell has a resistive sense element (RSE) coupled to a switching device, the RSE having a hard programming direction and an easy programming direction opposite the hard programming direction. A voltage boosting circuit includes a capacitor which adds charge to a nominal non-zero voltage supplied by a voltage source to a node to generate a temporarily boosted voltage. The boosted voltage is applied to the switching device when the RSE is programmed in the hard programming direction.

摘要翻译： 非易失性存储单元中的写入电流补偿的装置和方法，例如但不限于自旋转矩传递随机存取存储器（STRAM）或电阻随机存取存储器（RRAM）。 根据一些实施例，非易失性存储器单元具有耦合到开关器件的电阻感测元件（RSE），RSE具有硬编程方向和与硬编程方向相反的简单编程方向。 升压电路包括电容器，该电容器将电压加到由电压源向节点提供的标称非零电压以产生暂时提升的电压。 当RSE在硬编程方向编程时，升压电压施加到开关器件。

公开(公告)号：US20110058405A1

公开(公告)日：2011-03-10

申请号：US12946582

申请日：2010-11-15

申请人： Yiran Chen ,  Hai Li ,  Wenzhong Zhu ,  Xiaobin Wang ,  Ran Wang ,  Harry Hongyue Liu

发明人： Yiran Chen ,  Hai Li ,  Wenzhong Zhu ,  Xiaobin Wang ,  Ran Wang ,  Harry Hongyue Liu

IPC分类号： G11C11/16 ,  G11C11/21 ,  G11C7/06

CPC分类号： G11C7/062 ,  G11C11/1673 ,  G11C11/1693 ,  G11C13/004 ,  G11C2013/0057 ,  G11C2207/063

摘要： Various embodiments of the present invention are generally directed to a method and apparatus for sensing a programmed state of a memory cell, such as a spin-torque transfer random access memory (STRAM) cell. A first read current is applied to the memory cell to generate a first voltage. A second read current is subsequently applied to the memory cell to generate a second voltage, with the second read current being proportional in magnitude to the first read current. A comparison is made between the first and second voltages to determine the programmed state of the memory cell.

摘要翻译： 本发明的各种实施例通常涉及用于感测诸如自旋扭矩传递随机存取存储器（STRAM）单元的存储器单元的编程状态的方法和装置。 将第一读取电流施加到存储器单元以产生第一电压。 随后将第二读取电流施加到存储器单元以产生第二电压，其中第二读取电流在幅度上与第一读取电流成比例。 在第一和第二电压之间进行比较以确定存储器单元的编程状态。

公开(公告)号：US07855923B2

公开(公告)日：2010-12-21

申请号：US12426098

申请日：2009-04-17

申请人： Hai Li ,  Yiran Chen ,  Harry Hongyue Liu ,  Henry Huang ,  Ran Wang

发明人： Hai Li ,  Yiran Chen ,  Harry Hongyue Liu ,  Henry Huang ,  Ran Wang

IPC分类号： G11C5/14 ,  G11C8/00 ,  G11C11/00 ,  G11C11/14

CPC分类号： G11C8/08 ,  G11C11/1659 ,  G11C11/1675 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2013/0071

摘要： Apparatus and method for write current compensation in a non-volatile memory cell, such as but not limited to spin-torque transfer random access memory (STRAM) or resistive random access memory (RRAM). In accordance with some embodiments, a non-volatile memory cell has a resistive sense element (RSE) coupled to a switching device, the RSE having a hard programming direction and an easy programming direction opposite the hard programming direction. A voltage boosting circuit includes a capacitor which adds charge to a nominal non-zero voltage supplied by a voltage source to a node to generate a temporarily boosted voltage. The boosted voltage is applied to the switching device when the RSE is programmed in the hard programming direction.

摘要翻译： 非易失性存储单元中的写入电流补偿的装置和方法，例如但不限于自旋转矩传递随机存取存储器（STRAM）或电阻随机存取存储器（RRAM）。 根据一些实施例，非易失性存储器单元具有耦合到开关器件的电阻感测元件（RSE），RSE具有硬编程方向和与硬编程方向相反的简单编程方向。 升压电路包括电容器，该电容器将电压加到由电压源向节点提供的标称非零电压以产生暂时提升的电压。 当RSE在硬编程方向编程时，升压电压施加到开关器件。

公开(公告)号：US07830700B2

公开(公告)日：2010-11-09

申请号：US12269564

申请日：2008-11-12

申请人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li

发明人： Yiran Chen ,  Daniel S. Reed ,  Yong Lu ,  Harry Hongyue Liu ,  Hai Li

IPC分类号： G11C11/00

CPC分类号： G11C8/12 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0088 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/79

摘要： Various embodiments of the present invention are generally directed to a method and apparatus for carrying out a partial block update operation upon a resistive sense memory (RSM) array, such as formed from STRAM or RRAM cells. The RSM array is arranged into multi-cell blocks (sectors), each block having a physical block address (PBA). A first set of user data is written to a selected block at a first PBA. A partial block update operation is performed by writing a second set of user data to a second block at a second PBA, the second set of user data updating a portion of the first set of user data in the first PBA. The first and second blocks are thereafter read to retrieve the second set of user data and a remaining portion of the first set of user data.

摘要翻译： 本发明的各种实施例总体上涉及一种用于在诸如由STRAM或RRAM单元形成的电阻式感测存储器（RSM）阵列上执行部分块更新操作的方法和装置。 RSM阵列被布置成多小区块（扇区），每个块具有物理块地址（PBA）。 第一组用户数据在第一PBA被写入所选择的块。 通过在第二PBA将第二组用户数据写入第二块来执行部分块更新操作，第二组用户数据更新第一PBA中第一组用户数据的一部分。 然后读取第一和第二块以检索第二组用户数据和第一组用户数据的剩余部分。