公开(公告)号：US11315009B2

公开(公告)日：2022-04-26

申请号：US15449071

申请日：2017-03-03

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Brent Buchanan ,  Miao Hu ,  John Paul Strachan

IPC: G06N3/063 ,  G11C13/00 ,  H03M1/12 ,  G06F7/544

Abstract: An example electronic device includes a crossbar array, row driver circuitry, and column output circuits for each of the column lines of the crossbar array. The crossbar array may include row lines, column lines, and memristors that each are connected between one of the row lines and one of the column lines. The row driver circuitry may be to apply a plurality of analog voltages to a first node during a plurality of time periods, respectively, and, for each of the row lines, selectively connect the row line to the first node during one of the plurality of time periods based on a digital input vector. The column output circuits may each include: an integration capacitor, a switch that is controlled by an integration control signal, and current mirroring circuitry. The current mirroring circuitry may be to, when the switch is closed, flow an integration current to or from an electrode of the integration capacitor whose magnitude mirrors a current flowing on the corresponding column line. The integration control signal may be to close the switch for a specified amount of time during each of the plurality of time periods.

公开(公告)号：US11294763B2

公开(公告)日：2022-04-05

申请号：US16115100

申请日：2018-08-28

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： John Paul Strachan ,  Catherine Graves ,  Dejan S. Milojicic ,  Paolo Faraboschi ,  Martin Foltin ,  Sergey Serebryakov

IPC: G06F11/00 ,  G06F11/10 ,  G11C29/52

Abstract: A computer system includes multiple memory array components that include respective analog memory arrays which are sequenced to implement a multi-layer process. An error array data structure is obtained for at least a first memory array component, and from which a determination is made as to whether individual nodes (or cells) of the error array data structure are significant. A determination can be made as to any remedial operations that can be performed to mitigate errors of significance.

公开(公告)号：US11289162B2

公开(公告)日：2022-03-29

申请号：US16862997

申请日：2020-04-30

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： John Paul Strachan ,  Catherine Graves ,  Can Li

IPC: G11C15/04

Abstract: An analog content addressable memory cell includes a match line, a high side, and a low side. The high side encodes a high bound on a range of values and includes a first three terminal memory device. The first three terminal memory device includes a first gate that sets a high voltage bound of the first three terminal memory device. Specifically, an input voltage applied at the first gate of the first memory device, if higher than the high voltage bound, turns the first memory device ON which discharges the match line. Similarly, the low side encodes a lower bound on a range of values and includes a second three terminal memory device. The second three terminal memory device includes a second gate that sets a low voltage bound of the second three terminal memory device. Specifically, an input voltage applied at the second gate of the second memory device, if lower than the low voltage bound, turns the first memory device ON which discharges the match line.

公开(公告)号：US20210327508A1

公开(公告)日：2021-10-21

申请号：US17302439

申请日：2021-05-03

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Can Li ,  Catherine Graves ,  John Paul Strachan

IPC: G11C15/04 ,  G11C15/00

Abstract: Systems are methods are provided for implementing an analog content addressable memory (analog CAM), which is particularly structured to allow for an amount of variance (fuzziness) in its search operations. The analog CAM may search for approximate matches with the data stored therein, or matches within a defined variance. Circuitry of the analog CAM may include transistor-source lines that receive search-variance parameters, and/or data lines that receive search-variance parameters explicitly within the search input data. The search-variance parameters may include an upper bound and a lower bound that define a range of values within the allotted amount of fuzziness (e.g., deviation from the stored value). The search-variance parameters may program (using analog approaches) the analog CAM to perform searches having a modifiable restrictiveness that is tuned dynamically, as defined by the input search-variance. Thus, highly efficient hardware for complex applications involving fuzziness are enabled.

公开(公告)号：US10998047B1

公开(公告)日：2021-05-04

申请号：US16744136

申请日：2020-01-15

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Can Li ,  Catherine Graves ,  John Paul Strachan

IPC: G11C15/04 ,  G11C15/00

Abstract: Systems are methods are provided for implementing an analog content addressable memory (analog CAM), which is particularly structured to allow for an amount of variance (fuzziness) in its search operations. The analog CAM may search for approximate matches with the data stored therein, or matches within a defined variance. Circuitry of the analog CAM may include transistor-source lines that receive search-variance parameters, and/or data lines that receive search-variance parameters explicitly within the search input data. The search-variance parameters may include an upper bound and a lower bound that define a range of values within the allotted amount of fuzziness (e.g., deviation from the stored value). The search-variance parameters may program (using analog approaches) the analog CAM to perform searches having a modifiable restrictiveness that is tuned dynamically, as defined by the input search-variance. Thus, highly efficient hardware for complex applications involving fuzziness are enabled.

公开(公告)号：US20210050060A1

公开(公告)日：2021-02-18

申请号：US16539868

申请日：2019-08-13

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Can Li ,  Catherine Graves ,  John Paul Strachan

IPC: G11C15/04 ,  G11C8/12 ,  G11C11/413 ,  G11C11/408

Abstract: A reprogrammable dot product engine ternary content addressable memory (DPE-TCAM) is provided. The DPE-TCAM comprises a TCAM crossbar array comprising a plurality of match lines and a plurality of search lines. Each search line and match line are coupled together by a memory cell. A plurality of search line drivers are configured to apply a voltage signal to the search lines representing bits of a search word. Current sensing circuitry is coupled to the output of the plurality of match lines and configured to sense a current on the match lines, the sensed current indicating whether the search word and a stored word matched and, if not, the degree of mismatch between the two words.

公开(公告)号：US20210036058A1

公开(公告)日：2021-02-04

申请号：US17041382

申请日：2018-04-27

Applicant: HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP

Inventor： Amit S. Sharma ,  John Paul Strachan ,  Martin Foltin

IPC: H01L27/24 ,  H01L29/161 ,  H01L29/808 ,  H01L21/02 ,  H01L29/66

Abstract: Devices and methods are provided, In one aspect, a device for driving a memristor array includes a substrate including a well having a bottom layer, a first wall and a second wall. The substrate is formed of a strained layer of a first semiconductor material. A vertical JFET is formed in the well. The vertical JFET includes a vertical gate region formed in a middle portion of the well with a gate region height less than a depth of the well. A channel region is formed of an epitaxial layer of a second semiconductor wrapped around the vertical gate region. Vertical source regions are formed on both sides of a first end of the vertical gate region, and vertical drain regions are formed on both sides of a second end of the vertical gate region.

公开(公告)号：US20200285779A1

公开(公告)日：2020-09-10

申请号：US16291094

申请日：2019-03-04

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Martin Foltin ,  Aalap Tripathy ,  Harvey Edward White, JR. ,  John Paul Strachan

IPC: G06F21/76 ,  G06F21/55 ,  H04L29/06

Abstract: Examples described herein relate to a security system consistent with the disclosure. For instance, the security system may comprise a sensor interface bridge connecting a gateway to an input/output (I/O) card, a Field Programmable Gate Array (FPGA) to scan data to detect an anomaly in the data while the data is in the sensor interface bridge, where a learning neural network accelerator Application-Specific Integrated Circuit (ASIC) is integrated with the FPGA and send the data without an anomaly to the gateway.

公开(公告)号：US10770140B2

公开(公告)日：2020-09-08

申请号：US16065771

申请日：2016-01-27

Applicant: Hewlett Packard Enterprise Development LP

Inventor： John Paul Strachan ,  Brent Buchanan ,  Le Zheng

IPC: G11C13/00 ,  G11C11/56

Abstract: The present disclosure provides a memristive array. The array includes a number of memristive devices. A memristive device is switchable between states and is to store information. The memristive array also includes a parallel reset control device coupled to the number of memristive devices in parallel. The parallel reset control device regulates a resetting operation for the number of memristive devices by regulating current flow through target memristive devices.

公开(公告)号：US20200242447A1

公开(公告)日：2020-07-30

申请号：US16260898

申请日：2019-01-29

Applicant: Hewlett Packard Enterprise Development LP

Inventor： Suhas Kumar ,  Thomas Van Vaerenbergh ,  John Paul Strachan

IPC: G06N3/04 ,  G06N3/08 ,  G06N3/063

Abstract: Recurrent neural networks, and methods therefor, are provided with diagonal and programming fluctuation to find energy global minima. The method may include storing the matrix of weights in memory cells of a crossbar array of a recursive neural network prior to operation of the recursive neural network; altering the weights according to a probability distribution; setting the weights to non-zero values in at least one of the memory cells in a diagonal of the memory cells in the crossbar array; and operating the recursive neural network.