公开(公告)号：US20080129337A1

公开(公告)日：2008-06-05

申请号：US11933311

申请日：2007-10-31

申请人： Jason Redgrave ,  Brad Hutchings ,  Herman Schmit ,  Steven Teig

发明人： Jason Redgrave ,  Brad Hutchings ,  Herman Schmit ,  Steven Teig

IPC分类号： H03K19/0175

CPC分类号： H03K19/1737 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17748 ,  H03K19/17796

摘要： Some embodiments of the invention provide a configurable integrated circuit (“IC”). This IC includes several configurable circuits for receiving configuration data and configurably performing a set of operations based on the configuration data. It also includes several hybrid circuits. Each particular hybrid circuit can interchangeably perform as either a logic circuit or an interconnect circuit in the configurable IC.

摘要翻译： 本发明的一些实施例提供了可配置的集成电路（“IC”）。 该IC包括用于接收配置数据并且可配置地基于配置数据执行一组操作的多个可配置电路。 它还包括几个混合电路。 每个特定的混合电路可以互换地作为可配置IC中的逻辑电路或互连电路执行。

公开(公告)号：US20080030227A1

公开(公告)日：2008-02-07

申请号：US11871944

申请日：2007-10-12

申请人： Steven Teig ,  Herman Schmit ,  Jason Redgrave

发明人： Steven Teig ,  Herman Schmit ,  Jason Redgrave

IPC分类号： H03K19/177

CPC分类号： H03K19/17756 ,  H03K19/17776

摘要： Some embodiments provide a reconfigurable IC that includes several sections. Each section includes several configurable circuits, each of which configurably performs a set of operations. Each section stores multiple configuration data sets for each configurable circuit. Each configuration data set for a particular configurable circuit specifies the operation that the particular configurable circuit has to perform from the circuit's set of operations, where the configurable circuits of at least two different sections change configuration data sets at two different reconfiguration rates.

摘要翻译： 一些实施例提供了包括几个部分的可重新配置的IC。 每个部分包括几个可配置的电路，每个可配置电路可配置地执行一组操作。 每个部分存储每个可配置电路的多个配置数据集。 针对特定可配置电路的每个配置数据集指定特定可配置电路必须从电路的操作集合执行的操作，其中至少两个不同部分的可配置电路以两种不同的重新配置速率改变配置数据集。

公开(公告)号：US20080018359A1

公开(公告)日：2008-01-24

申请号：US11775218

申请日：2007-07-09

申请人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Huang ,  Jason Redgrave

发明人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Huang ,  Jason Redgrave

IPC分类号： H03K19/177

CPC分类号： H01L25/065 ,  H01L27/0207 ,  H01L27/11803 ,  H01L27/11898 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/15311 ,  H03K19/17736 ,  H03K19/17796 ,  H01L2924/00014 ,  H01L2924/00

摘要： Some embodiments provide a configurable IC that includes several configurable tiles. The configurable tiles include several interior tiles within the interior of an arrangement of configurable tiles. The arrangement has several sides that define the exterior boundary of the arrangement. In some embodiments, each configurable interior tile includes a set of configurable logic circuits, a set of configurable input-select circuits for selecting inputs to the configurable logic circuits, and a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits. The set of configurable input-select circuits in each interior tile has a set of inputs that are supplied by a set of asymmetric locations in the configurable IC. Any distance between any input-select circuit in any interior tile and any boundary-defining side of the tile arrangement is greater than any distance between any particular input-select circuit in any interior tile and any circuit that provides an input to the particular input-select circuit. Also, in some embodiments, each configurable interior tile includes a set of configurable logic circuits and a set of configurable routing interconnect circuits for routing signals between the configurable logic circuits. The set of configurable logic circuits in each interior tile has a set of outputs that are supplied to a set of asymmetric locations in the configurable IC. Any distance between any logic circuit in any interior tile and any boundary-defining side of the tile arrangement is greater than any distance between any particular logic circuit in any interior tile and any circuit that receives an output of the particular logic circuit. In some embodiments, the set of asymmetric locations is a set of locations that includes at least one location that has no symmetrical relationship with any other location in the set. In some embodiments, each input-select circuit has at least one output that is supplied to one configurable logic circuit.

公开(公告)号：US07295037B2

公开(公告)日：2007-11-13

申请号：US11082193

申请日：2005-03-15

申请人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Renfu Huang

发明人： Herman Schmit ,  Steven Teig ,  Brad Hutchings ,  Randy Renfu Huang

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17796

摘要： Some embodiments provide a configurable integrated circuit (“IC”) that includes several configurable tiles arranged in a tile arrangement. Each configurable tile has a set of configurable logic circuits and a set of configurable routing circuits for routing signals between configurable logic circuits. At least a first routing circuit of a first tile has at least one direct connection with a second circuit of a second tile that does not neighbor the first tile and that is not aligned horizontally or vertically with the first tile in the tile arrangement.

摘要翻译： 一些实施例提供了一种可配置集成电路（“IC”），其包括以瓦片排列方式布置的多个可配置瓦片。 每个可配置的瓦片具有一组可配置逻辑电路和一组用于在可配置逻辑电路之间路由信号的可配置路由电路。 第一瓦片的至少第一路由电路具有与第二瓦片的第二电路的至少一个直接连接，第二瓦片不邻近第一瓦片，并且不与水平或垂直对准在瓦片布置中的第一瓦片。

公开(公告)号：US20070241788A1

公开(公告)日：2007-10-18

申请号：US11565607

申请日：2006-11-30

申请人： Herman Schmit ,  Steven Teig

发明人： Herman Schmit ,  Steven Teig

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17748

摘要： Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes first and second circuits. The first circuit is a logic circuit for receiving configuration data sets and performing at least a first function when receiving a first configuration data set and a second function when receiving a second configuration data set. The second circuit communicatively couples to the first logic circuit. The second circuit is for supplying configuration data sets to the first logic circuit. The second circuit has a first set of input terminals. The integrated circuit also has a second set of input terminals for carrying data. Several the second set of input terminals overlap several of the first set of input terminals. The IC also has a set of vias, where each via connects an input terminal in the first set with an input terminal in the second set.

摘要翻译： 本发明的一些实施例提供了一种可配置的集成电路（IC）。 IC包括第一和第二电路。 第一电路是用于接收配置数据集并且当接收第二配置数据集时接收第一配置数据集和第二功能时执行至少第一功能的逻辑电路。 第二电路通信耦合到第一逻辑电路。 第二电路用于将配置数据组提供给第一逻辑电路。 第二电路具有第一组输入端子。 集成电路还具有用于承载数据的第二组输入端子。 几个第二组输入端与第一组输入端重叠。 IC还具有一组通孔，其中每个通孔将第一组中的输入端与第二组中的输入端连接。

公开(公告)号：US20070241787A1

公开(公告)日：2007-10-18

申请号：US11565592

申请日：2006-11-30

申请人： Herman Schmit ,  Michael Butts ,  Brad L. Hutchings ,  Steven Teig

发明人： Herman Schmit ,  Michael Butts ,  Brad L. Hutchings ,  Steven Teig

IPC分类号： H03K19/173

CPC分类号： H03K19/17748

摘要： Some embodiments of the invention provide a first configurable integrated circuit (IC) that has a first configurable IC design. The first configurable IC implements a second IC design that is specified for a second IC that is to operate a particular design rate. The first configurable IC includes several configurable logic circuits. Each configurable logic circuit can configurably perform a set of functions. The IC also includes several configurable interconnect circuits that configurably couple the logic circuits. At least several configurable circuits can reconfigure faster than the particular design rate.

摘要翻译： 本发明的一些实施例提供了具有第一可配置IC设计的第一可配置集成电路（IC）。 第一个可配置IC实现了第二个IC设计，该第二个IC设计指定用于操作特定设计速率的第二个IC。 第一个可配置的IC包括几个可配置的逻辑电路。 每个可配置的逻辑电路可配置地执行一组功能。 IC还包括可配置地耦合逻辑电路的几个可配置互连电路。 至少几个可配置电路可以比特定设计速率重新配置更快。

公开(公告)号：US20070241780A1

公开(公告)日：2007-10-18

申请号：US11081877

申请日：2005-03-15

申请人： Steven Teig ,  Herman Schmit ,  Jason Redgrave

发明人： Steven Teig ,  Herman Schmit ,  Jason Redgrave

IPC分类号： H03K19/177

CPC分类号： H03K19/17756 ,  H03K19/17776

摘要： Some embodiments provide a reconfigurable IC that includes several sections. Each section includes several configurable circuits, each of which of which configurably performs a set of operations, Each section stores multiple configuration data sets for each configurable circuit. Each configuration data set for a particular configurable circuit specifies the operation that the particular configurable circuit has to perform from the circuit's set of operations, where the configurable circuits of at least two different sections change configuration data sets at two different reconfiguration rates.

摘要翻译： 一些实施例提供了包括几个部分的可重新配置的IC。 每个部分包括多个可配置电路，每个可配置电路可配置地执行一组操作。每个部分存储每个可配置电路的多个配置数据集。 针对特定可配置电路的每个配置数据集指定特定可配置电路必须从电路的操作集合执行的操作，其中至少两个不同部分的可配置电路以两种不同的重新配置速率改变配置数据集。

公开(公告)号：US07262633B1

公开(公告)日：2007-08-28

申请号：US11271080

申请日：2005-11-11

申请人： Herman Schmit ,  Steven Teig

发明人： Herman Schmit ,  Steven Teig

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17796

摘要： Some embodiments provide a via programmable gate array (“VPGA”) with several configurable circuits arranged in a configurable circuit arrangement. At least some of the configurable circuits are via programmable (“VP”) configured circuits. In some embodiments, the configurable circuit arrangement is a configurable circuit arrangement that includes numerous (e.g., 50, 100, etc.) configurable circuits that are arranged in several rows and columns. This circuit arrangement also includes several bit lines, where at least one the bit line provides a configuration value to at least one configurable circuit. In some embodiments, at least some bit lines transverse along more than one column or row in the circuit arrangement.

摘要翻译： 一些实施例提供具有以可配置电路布置布置的多个可配置电路的通孔可编程门阵列（“VPGA”）。 至少一些可配置电路通过可编程（“VP”）配置电路。 在一些实施例中，可配置电路装置是可配置的电路装置，其包括布置成多行和多列的许多（例如，50,100等）可配置电路。 该电路布置还包括几个位线，其中至少一个位线向至少一个可配置电路提供配置值。 在一些实施例中，至少一些位线沿着电路装置中的多于一列或多行而横越。

公开(公告)号：US20070075737A1

公开(公告)日：2007-04-05

申请号：US11467918

申请日：2006-08-28

申请人： Herman Schmit ,  Michael Butts ,  Brad Hutchings ,  Steven Teig

发明人： Herman Schmit ,  Michael Butts ,  Brad Hutchings ,  Steven Teig

IPC分类号： H03K19/177

CPC分类号： H03K19/17736 ,  H03K19/17744 ,  H03K19/17776

摘要： Some embodiments of the invention provide configurable integrated circuit (IC) that has a first interface rate for exchanging signals with a circuit outside of the configurable IC. The configurable IC has an array of configurable circuits. The array includes several configurable logic and interconnect circuits. Each configurable logic circuit can configurably perform a set of functions. The configurable interconnect circuits can configurably couple the logic circuits. At least several of the configurable circuits can be reconfigured faster than the first rate.

摘要翻译： 本发明的一些实施例提供了具有用于与可配置IC外部的电路交换信号的第一接口速率的可配置集成电路（IC）。 可配置IC具有可配置电路阵列。 该阵列包括多个可配置的逻辑和互连电路。 每个可配置的逻辑电路可配置地执行一组功能。 可配置互连电路可配置地耦合逻辑电路。 至少几个可配置电路可以重新配置得比第一个速率快。

公开(公告)号：US07167025B1

公开(公告)日：2007-01-23

申请号：US10883051

申请日：2004-06-30

申请人： Herman Schmit ,  Michael Butts ,  Brad L. Hutchings ,  Steven Teig

发明人： Herman Schmit ,  Michael Butts ,  Brad L. Hutchings ,  Steven Teig

IPC分类号： H01L25/00 ,  H03K19/173 ,  H03K5/01 ,  H03K17/50 ,  G06F7/38

CPC分类号： G06F17/5068 ,  H03K19/17748 ,  H03K19/17752 ,  H03K19/17776

摘要： Some embodiments of the invention provide a configurable integrated circuit (IC). The IC includes at least fifty configurable circuits arranged in an array having a plurality of rows and a plurality of columns. Each configurable circuit for configurably performing a set of operations. At least a first configurable circuit reconfigures at a first reconfiguration rate. The first configurable circuit performs a different operation each time the first configurable circuit is reconfigured. The reconfiguration of the first configurable circuit does not follow any sequential progression through the set of operations of the first configurable circuit.

摘要翻译： 本发明的一些实施例提供了一种可配置的集成电路（IC）。 IC包括布置在具有多个行和多个列的阵列中的至少五十个可配置电路。 每个可配置电路，用于可配置地执行一组操作。 至少第一可配置电路以第一重新配置速率重新配置。 第一可配置电路在每次重新配置第一可配置电路时执行不同的操作。 第一可配置电路的重新配置不遵循通过第一可配置电路的一组操作的任何顺序进行。