公开(公告)号：US06877024B1

公开(公告)日：2005-04-05

申请号：US09666086

申请日：2000-09-21

申请人： Kazunori Ukigawa ,  Hiroki Yamashita ,  Akira Yamada

发明人： Kazunori Ukigawa ,  Hiroki Yamashita ,  Akira Yamada

IPC分类号： G06F13/00 ,  G06F15/00 ,  G06F15/16 ,  H04L12/18

CPC分类号： H04L12/1827

摘要： A server device having a content provider, a voice provider and an access number counter, etc. is arranged on the Internet. The content provider provides terminal devices connected to the Internet with the contents (e.g., contents of a chat) which are updated at predetermined intervals. The access number counter counts the number of terminal devices which have currently logged in to the contents provided by the content provider and have not logged out therefrom. The voice provider sets a voice level in accordance with a value counted by the access number counter, every time new contents are provided by the content provider, and provides voice data.

摘要翻译： 具有内容提供商，语音提供者和接入号码计数器等的服务器设备被布置在因特网上。 内容提供商提供连接到因特网的终端设备，其内容（例如聊天的内容）以预定间隔被更新。 访问号码计数器计数当前登录到由内容提供商提供的内容并且尚未从其注销的终端设备的数量。 语音提供者根据由接入号码计数器计数的值，每当内容提供商提供新内容时设置语音电平，并提供话音数据。

公开(公告)号：US06330703B1

公开(公告)日：2001-12-11

申请号：US09041121

申请日：1998-03-12

申请人： Tatsuya Saito ,  Masayoshi Yagyu ,  Hiroki Yamashita ,  Tsuneyo Chiba ,  Masakazu Yamamoto

发明人： Tatsuya Saito ,  Masayoshi Yagyu ,  Hiroki Yamashita ,  Tsuneyo Chiba ,  Masakazu Yamamoto

IPC分类号： G06F1750

CPC分类号： G01R31/3004 ,  G06F2217/78

摘要： A logic circuit determines the power consumption of a semiconductor integrated device by taking into consideration the variation of the rate of operation. A control signal (TEST) is applied to each control signal input port (Tin) of flip-flop circuits of flip-flop circuit groups and a logic gate circuit having a plurality of input ports A and B in a combined circuit group. If the control signal (TEST) is low, both the flip-flop circuits and the logic gate circuit operate normally. However, if the control signal (TEST) is high, each of them performs the power consumption test. Regardless of the value of input signals applied to input ports D1 and D2 of the flip-flop circuits, the flip-flop circuits are controlled to have a repetitive output signal of high and low levels at ports Q1 and Q2, in synchronism with a clock signal. Through this operation test, operational failure is reduced and the quality of semiconductor chip production is guaranteed, because it is possible to predict accurately the power consumption when designing the logic circuit due to the relationship between the rate of operation and the power consumption.

摘要翻译： 逻辑电路通过考虑操作速率的变化来确定半导体集成器件的功耗。 控制信号（TEST）被施加到组合电路组中具有多个输入端口A和B的触发器电路组的触发器电路的每个控制信号输入端口（Tin）和逻辑门电路。 如果控制信号（TEST）低，触发器电路和逻辑门电路均正常工作。 但是，如果控制信号（TEST）为高，则进行功耗测试。 不管施加到触发器电路的输入端口D1和D2的输入信号的值如何，触发器电路被控制为具有在时钟Q1与Q2的端口Q1和Q2的高电平和低电平的重复输出信号 信号。 通过这种操作测试，可以降低运行故障，保证半导体芯片生产的质量，因为由于操作速率和功耗之间的关系，可以准确地预测设计逻辑电路时的功耗。

公开(公告)号：US06202168B1

公开(公告)日：2001-03-13

申请号：US09113332

申请日：1998-07-10

申请人： Tatsuya Saito ,  Tetsuya Umemura ,  Hiroki Yamashita

发明人： Tatsuya Saito ,  Tetsuya Umemura ,  Hiroki Yamashita

IPC分类号： G06F104

CPC分类号： H04L7/033 ,  G01R31/31908 ,  H04L7/0008 ,  H04L7/0041 ,  H04L7/04

摘要： The delay time for the transfer of data signals between pluralities of logic circuits is automatically regulated to be in a desired range. In order to regulate the delay time of the data signal transfer, a common standard signal SYNC is distributed to the logic circuits from a standard signal generator source. In the sending side of one logic circuit, the standard signal is applied through a selector circuit to a flip-flop circuit and then transferred to the receiving side of another logic circuit. Specifically, the transferred standard signal passes through a variable delay circuit to a flip flop circuit on the receiving side of the other logic circuit where it is compared with the standard signal received from the standard signal generator source, which has passed through a delay circuit of a standard delay value. The result of the comparison is used to adjust the variable delay circuit that controls the delay time for the transferred standard signal. Once the variable delay circuit is adjusted with the standard signal, the selector selects normal data signals for transfer between the logic circuits with the appropriate delay. The standard signal can also be used to synchronize the generation of test pattern signals generated in each of the logic circuits.

摘要翻译： 在多个逻辑电路之间传送数据信号的延迟时间被自动调节到期望的范围内。 为了调节数据信号传输的延迟时间，从标准信号发生器源将公共标准信号SYNC分配给逻辑电路。 在一个逻辑电路的发送侧，通过选择器电路将标准信号施加到触发器电路，然后传送到另一逻辑电路的接收侧。 具体地，传送的标准信号通过可变延迟电路到另一个逻辑电路的接收侧的触发电路，与从标准信号发生器源接收的标准信号进行比较，该标准信号已通过延迟电路 标准延迟值。 比较结果用于调整控制传输标准信号的延迟时间的可变延迟电路。 一旦用标准信号调整可变延迟电路，选择器就选择正常的数据信号，以便在逻辑电路之间以适当的延迟进行传输。 标准信号也可用于同步在每个逻辑电路中产生的测试图形信号的产生。

公开(公告)号：US06191647B1

公开(公告)日：2001-02-20

申请号：US09220372

申请日：1998-12-24

申请人： Katsuya Tanaka ,  Masayoshi Yagyu ,  Tatsuya Saito ,  Tetsuya Uemura ,  Tomohisa Iwanaga ,  Hiroki Yamashita ,  Takeshi Kato

发明人： Katsuya Tanaka ,  Masayoshi Yagyu ,  Tatsuya Saito ,  Tetsuya Uemura ,  Tomohisa Iwanaga ,  Hiroki Yamashita ,  Takeshi Kato

IPC分类号： H03K500

CPC分类号： H03K19/00346

摘要： A condenser having a huge area is required to reduce a noise on LSI power supply nets (−&Dgr;VDD) of an integrated circuit because a bypass condenser can only utilize a part of accumulated electric charges. A noise of LSI power supply nets is suppressed by generating a noise of a reversed polarity (+&Dgr;VDD) to the noise on the LSI power supply nets (−&Dgr;VDD), based upon a noise reducing circuit discharging a condenser charged with a high voltage. A noise reduction effect equivalent to a bypass condenser having a large capacity is obtained even when a condenser having a small capacity is used.

摘要翻译： 需要具有巨大面积的电容器来减小集成电路的LSI电源网（-DELTAVDD）上的噪声，因为旁路电容器只能使用一部分累积的电荷。 基于降低放电高电压的电容器的噪声降低电路，对LSI电源网（-DELTAVDD）的噪声产生相反极性（+ DELTAVDD）的噪声来抑制LSI电源网的噪声。 即使使用容量小的冷凝器，也能够获得与大容量的旁路电容器相当的噪声降低效果。

公开(公告)号：US5521536A

公开(公告)日：1996-05-28

申请号：US286270

申请日：1994-08-05

申请人： Hiroki Yamashita ,  Hiroyuki Itoh ,  Atsumi Kawata ,  Tatsuya Saitoh ,  Keiichirou Nakanishi ,  Rieko Ishida ,  Tsuneyo Chiba

发明人： Hiroki Yamashita ,  Hiroyuki Itoh ,  Atsumi Kawata ,  Tatsuya Saitoh ,  Keiichirou Nakanishi ,  Rieko Ishida ,  Tsuneyo Chiba

IPC分类号： H03K19/0175

CPC分类号： H03K19/017545

摘要： In signal transmission lines among logic circuits employed in a semiconductor integrated circuit device, a voltage driver circuit is provided with such a wiring whose length is short, and the function of the signal receiving circuit is achieved by a logic circuit capable of responding to a voltage appearing at a terminal of the wiring. On the other hand, a source terminal of such a wiring whose length is long and whose resistance is high, is voltage-driven by the voltage driver circuit in response to the output voltage of the logic circuit. A current sense circuit is provided with a terminal of this long length wiring, which senses a current flowing through this long length wiring to be converted into a voltage. Both an output resistance of the voltage driver circuit and an input resistance of the current sense circuit are made lower than a DC resistance of this long length wiring.

摘要翻译： 在半导体集成电路装置中使用的逻辑电路之间的信号传输线中，电压驱动电路具有长度短的布线，信号接收电路的功能由能够对电压进行响应的逻辑电路 出现在接线端子处。 另一方面，长度长且电阻较高的布线的源极端子由电压驱动电路根据逻辑电路的输出电压进行电压驱动。 电流检测电路设置有该长度布线的端子，该端子感测流过该长度布线的电流，以转换成电压。 电压驱动电路的输出电阻和电流检测电路的输入电阻均低于该长度布线的直流电阻。

公开(公告)号：US5426784A

公开(公告)日：1995-06-20

申请号：US16532

申请日：1993-02-11

申请人： Atsumi Kawata ,  Hirotoshi Tanaka ,  Hiroki Yamashita ,  Kenji Nagai ,  Minoru Yamada ,  Nobuhiro Taniguchi

发明人： Atsumi Kawata ,  Hirotoshi Tanaka ,  Hiroki Yamashita ,  Kenji Nagai ,  Minoru Yamada ,  Nobuhiro Taniguchi

IPC分类号： G06F5/00 ,  H03M9/00 ,  G06F1/04

CPC分类号： H03M9/00

摘要： A shift register 10 receives serial data and outputs parallel data in synchronism with the timing of the serial data received. A shift register group 20, 21 receives bit outputs of the parallel data from the shift register 10. The number of bits of shift registers 20, 21 in the shift register group is set in a certain condition that corresponds to the bit outputs of the parallel data from the shift register 10. A plurality of coincidence circuits 107, 108 are provided, which detects agreement between a preset data starting pattern and the bit arrangement of the data in the shift register group. A selector 306 selects a set of parallel outputs from the shift register group according to the output signal from the coincidence circuits 107, 108. Thus only the shift register 10, performs high-speed operations at the same timing as the received serial data, and the other circuits operate at slower speeds whose timing is several times longer than that of the serial data received, thereby eliminating complex timing and averting difficulty control logic.

摘要翻译： 移位寄存器10接收串行数据并且与所接收的串行数据的定时同步地输出并行数据。 移位寄存器组20,21从移位寄存器10接收并行数据的位输出。移位寄存器组中的移位寄存器20,21的位数被设定在对应于并行的位输出的一定条件 提供了多个符合电路107,108，其检测预设数据起始模式与移位寄存器组中的数据的位排列之间的一致性。 选择器306根据来自符合电路107,108的输出信号从移位寄存器组中选择一组并行输出。因此，只有移位寄存器10在与所接收的串行数据相同的定时进行高速操作，以及 其他电路以较慢的速度工作，其定时比接收的串行数据的时间长几倍，从而消除复杂的时序并避免难度控制逻辑。

公开(公告)号：US5396198A

公开(公告)日：1995-03-07

申请号：US118178

申请日：1993-09-09

申请人： Hiroki Yamashita ,  Hiroyuki Itoh ,  Keiichirou Nakanishi ,  Tatsuya Saitoh ,  Tohru Kobayashi ,  Satoru Isomura

发明人： Hiroki Yamashita ,  Hiroyuki Itoh ,  Keiichirou Nakanishi ,  Tatsuya Saitoh ,  Tohru Kobayashi ,  Satoru Isomura

IPC分类号： H01L23/528 ,  H01L23/66 ,  H01P5/12 ,  H01P1/26

CPC分类号： H01L23/5286 ,  H01L23/66 ,  H01L2223/6627 ,  H01L2924/0002 ,  H01L2924/1903 ,  H01L2924/3011

摘要： A power source wiring supplies power to individual electronic circuits constituting an electronic circuit device. Load circuits are connected to the power source wiring within the range of an arrival time of a voltage noise occurring in the power source wiring in a time of about a half of a pulse width of a noise current at the time of the operation of the electronic circuit. Each of these load circuits includes a series circuit of a resistance and a capacitance.

摘要翻译： 电源线为构成电子电路装置的各电子线路供电。 负载电路在电子线路中发生的电压噪声的到达时间的范围内连接到电源布线，时间为电子操作时的噪声电流的脉冲宽度的大约一半 电路。 这些负载电路中的每一个都包括电阻和电容的串联电路。

公开(公告)号：US5241355A

公开(公告)日：1993-08-31

申请号：US957440

申请日：1992-10-07

申请人： Hiroki Yamashita ,  Yoshihito Hirano

发明人： Hiroki Yamashita ,  Yoshihito Hirano

IPC分类号： G03G15/00

CPC分类号： G03G15/6541 ,  G03G15/6582 ,  G03G2215/00426 ,  G03G2215/0054 ,  G03G2215/00556 ,  G03G2215/00818 ,  G03G2215/00827

摘要： A copying apparatus having a stapling function and a punching function. When the allowable sheet capacity for stapling is X and the allowable sheet capacity for punching is Y and the both the staple and punch modes are selected, the number of processable sheets in the staple/punch mode is determined by setting the value X or Y, whichever is smaller, as the sheet capacity of the device. While processing is on-going in the staple/punch mode, the staple/punch mode is cancelled when the number of copy sheets exceeds the capacity of the mode.

摘要翻译： 具有装订功能和冲孔功能的复印装置。 当装订的允许纸张容量为X，冲孔允许的纸张容量为Y，并且选择订书钉和打孔模式时，通过设定值X或Y来确定订书钉/打孔模式中的可处理纸张的数量， 以较小者为准，作为设备的纸张容量。 当订书钉/打孔模式下正在进行处理时，当复印页数超过模式的容量时，订书钉/打孔模式将被取消。

公开(公告)号：US5053831A

公开(公告)日：1991-10-01

申请号：US311842

申请日：1989-02-17

申请人： Kuniaki Ishiguro ,  Takuma Ishikawa ,  Akiyoshi Johdai ,  Hiroki Yamashita

发明人： Kuniaki Ishiguro ,  Takuma Ishikawa ,  Akiyoshi Johdai ,  Hiroki Yamashita

IPC分类号： G03G15/00

CPC分类号： G03G15/6541 ,  G03G15/50 ,  G03G2215/00827

摘要： A copying machine having a sorter and a finisher is capable of operating in three different modes: a copying mode with sorting, a copying mode without sorting, and a stapling finish mode. When the stapling finish mode is selected, an automatic magnification selecting mode (AMS mode) is automatically chosen, wherein only copies of one size are made during the copying operation such that unsatisfactory stapling caused by copy sheets of differing size is prevented. Also, if one of a number of sorting bins of the copying machine is not being used while the copying machine is operating in the stapling finish mode, a copying operation can be carried out in the copying mode without sorting, utilizing that bin.

摘要翻译： 具有分拣机和整理机的复印机能够以三种不同的模式进行操作：具有分类的复印模式，无分类的复印模式和装订完成模式。 当选择装订完成模式时，自动选择自动倍率选择模式（AMS模式），其中在复印操作期间仅进行一种尺寸的复印，从而防止由不同尺寸的复印纸引起的不令人满意的装订。 此外，当复印机在装订完成模式下操作时，如果复印机的多个分拣机中的一个没有被使用，则可以在不进行分拣的复印模式中进行复印操作，利用该纸盒。