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    Integrated circuit device having different signal transfer circuits for wirings with different lengths
    2.
    发明授权
    Integrated circuit device having different signal transfer circuits for wirings with different lengths 失效
    具有不同长度的布线的不同信号传输电路的集成电路装置

    公开(公告)号：US5521536A

    公开(公告)日：1996-05-28

    申请号：US286270

    申请日：1994-08-05

    申请人： Hiroki Yamashita ,  Hiroyuki Itoh ,  Atsumi Kawata ,  Tatsuya Saitoh ,  Keiichirou Nakanishi ,  Rieko Ishida ,  Tsuneyo Chiba

    发明人： Hiroki Yamashita ,  Hiroyuki Itoh ,  Atsumi Kawata ,  Tatsuya Saitoh ,  Keiichirou Nakanishi ,  Rieko Ishida ,  Tsuneyo Chiba

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/017545

    摘要： In signal transmission lines among logic circuits employed in a semiconductor integrated circuit device, a voltage driver circuit is provided with such a wiring whose length is short, and the function of the signal receiving circuit is achieved by a logic circuit capable of responding to a voltage appearing at a terminal of the wiring. On the other hand, a source terminal of such a wiring whose length is long and whose resistance is high, is voltage-driven by the voltage driver circuit in response to the output voltage of the logic circuit. A current sense circuit is provided with a terminal of this long length wiring, which senses a current flowing through this long length wiring to be converted into a voltage. Both an output resistance of the voltage driver circuit and an input resistance of the current sense circuit are made lower than a DC resistance of this long length wiring.

    摘要翻译： 在半导体集成电路装置中使用的逻辑电路之间的信号传输线中，电压驱动电路具有长度短的布线，信号接收电路的功能由能够对电压进行响应的逻辑电路 出现在接线端子处。 另一方面，长度长且电阻较高的布线的源极端子由电压驱动电路根据逻辑电路的输出电压进行电压驱动。 电流检测电路设置有该长度布线的端子，该端子感测流过该长度布线的电流，以转换成电压。 电压驱动电路的输出电阻和电流检测电路的输入电阻均低于该长度布线的直流电阻。

    Semiconductor device using MIS capacitor
    3.
    发明授权
    Semiconductor device using MIS capacitor 失效
    半导体器件采用MIS电容器

    公开(公告)号：US5018000A

    公开(公告)日：1991-05-21

    申请号：US367046

    申请日：1989-06-16

    申请人： Toshio Yamada ,  Tohru Kobayashi ,  Hirotaka Nishizawa ,  Hiroyuki Itoh ,  Tatsuya Saitoh

    发明人： Toshio Yamada ,  Tohru Kobayashi ,  Hirotaka Nishizawa ,  Hiroyuki Itoh ,  Tatsuya Saitoh

    IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8222 ,  H01L27/06 ,  H03K17/60 ,  H03K19/003

    CPC分类号： H01L27/0647

    摘要： A MIS capacitor to be implemented in a semiconductor device employing various or predetermined circuits, has a dielectric side electrode which is in contact with a buried layer provided on a semiconductor substrate through a dielectric film and a buried layer-side electrode connected to the buried layer. The buried layer-side electrode of the MIS capacitor is connected to a low-impedance side of the circuit employed therewith. This structure, when connected as such, is capable of reducing the influence of noise attributed to an .alpha.-ray and thereby operating the circuit stably. The semiconductor device using a MIS capacitor invention is adaptable to an emitter follower circuit and various logic circuits for preventing malfunction resulting from .alpha.-ray radiation.

    摘要翻译： 在采用各种或预定电路的半导体器件中实现的MIS电容器具有通过电介质膜与设置在半导体衬底上的掩埋层接触的电介质侧电极和连接到掩埋层的掩埋层侧电极 。 MIS电容器的掩埋层侧电极与使用的电路的低阻抗侧连接。 当这样连接时，该结构能够减少归因于α射线的噪声的影响，从而稳定地操作电路。 使用MIS电容器发明的半导体器件适用于射极跟随器电路和用于防止由α射线辐射引起的故障的各种逻辑电路。

    Logic circuit
    5.
    发明授权
    Logic circuit 失效
    逻辑电路

    公开(公告)号：US5021686A

    公开(公告)日：1991-06-04

    申请号：US470322

    申请日：1990-01-25

    申请人： Atsumi Kawata ,  Hiroyuki Itoh ,  Hirotoshi Tanaka ,  Kazuhiro Yoshihara ,  Hiroki Yamashita

    发明人： Atsumi Kawata ,  Hiroyuki Itoh ,  Hirotoshi Tanaka ,  Kazuhiro Yoshihara ,  Hiroki Yamashita

    IPC分类号： H03K19/003 ,  H03K19/017 ,  H03K19/0952

    CPC分类号： H03K19/00384 ,  H03K19/01707 ,  H03K19/01721 ,  H03K19/0952

    摘要： A logic circuit, most suitable for the NOR gate, logic function and integration on a single chip with a plurality of such logic circuits and other digital circuits receiving the outputs of the logic circuits and the logic circuits themselves connected and cascade, wherein plural groups of input transistors are provided, with a load through the voltage source and one of the groups, field effect transistor between the voltage source and the other group, so that its gate is connected to the node between the load and first group and its source is connected to the output terminal, with the improvement being in finding a leakage load for the field effect transistor through the voltage source, providing a clamping circuit for the gate of the transistor. The clamping circuit can include a transistor having its gate connected to the output with a delay so that it will not come on until after a substantial portion of the rise time of the output has expired. An additional logic output may be taken from the gate of this transistor, preferably through a transistor to match the outputs, so that the logic circuit is provided with two independent outputs useful for providing adjacent logic or digital circuits with a conveniently close terminal for input, and further to take advantage of the isolation of the outputs by providing other directions for both outputs for circuit elements that must remain isolated, for example in cross coupling two logic circuits as a flipflop. One or more of the may be a field effect transistor, particularly provided with boot strapping. For otherwise identical logic circuits as a part of an overall integrated logic circuit, the clamping circuits may differ only with respect to matching respective output voltages or respective output currents with respective fan outs or other characteristics of load circuits to be driven by the outputs. Preferably, all of the elements are constructed of field effect transistors.

    摘要翻译： 逻辑电路，最适合于NOR门，逻辑功能，并且集成在具有多个这样的逻辑电路的单个芯片上，并且其它数字电路接收逻辑电路和逻辑电路本身连接和级联的输出，其中多组 提供输入晶体管，通过电压源和组中的一个负载，电压源和另一组之间的场效应晶体管，使得其栅极连接到负载和第一组之间的节点，并且其源极被连接 到输出端子，其改进在于通过电压源找到场效应晶体管的泄漏负载，为晶体管的栅极提供钳位电路。 钳位电路可以包括晶体管，其晶体管的栅极连接到输出端延迟，使得在输出的大部分上升时间到期之后，晶体管将不会进入。 可以从该晶体管的栅极获取额外的逻辑输出，优选地通过晶体管来匹配输出，使得逻辑电路具有两个独立的输出，用于向相邻的逻辑或数字电路提供方便的关闭端子用于输入， 并且还通过为必须保持隔离的电路元件的两个输出提供其它方向，例如将两个逻辑电路作为触发器交叉耦合，来利用输出的隔离。 一个或多个可以是场效应晶体管，特别是提供引导带。 对于作为整体集成逻辑电路的一部分的其他相同的逻辑电路，钳位电路可以相对于匹配相应的输出电压或相应的输出电流或相应的输出电流或者相应的输出电流驱动的负载电路的其他特性而不同。 优选地，所有元件由场效应晶体管构成。

    Transistor circuit with improved .alpha. ray resistant properties
    8.
    发明授权
    Transistor circuit with improved .alpha. ray resistant properties 失效
    具有改进的抗α射线特性的晶体管电路

    公开(公告)号：US4942320A

    公开(公告)日：1990-07-17

    申请号：US208118

    申请日：1988-06-17

    申请人： Hiroyuki Itoh ,  Toshio Yamada ,  Akira Masaki ,  Tohru Kobayashi

    发明人： Hiroyuki Itoh ,  Toshio Yamada ,  Akira Masaki ,  Tohru Kobayashi

    IPC分类号： H03K17/16 ,  H03K19/003 ,  H03K19/086

    CPC分类号： H03K17/16 ,  H03K19/0033 ,  H03K19/086

    摘要： A transistor circuit of this invention comprises a first transistor for receiving a first bias at its base, resistor means connected to the collector of the first transistor and clamp means connected to the junction between the first transistor and the resistor means, and obtains an output from a terminal of the resistor on the opposite to its junction with the first transistor. When a noise current due to .alpha. rays develops in the first transistor and the output is lowered, the clamp means operates in such a manner that the current flows through the clamp means and prevents the change of the output. The transistor circuit of this invention is connected to a resistor or a transistor and operates as a constant current circuit for supplying a current to the resistor or the transistor so that the current flowing therethrough becomes constant. For example, it is used as a constant current source of an emitter follower to constitute a level shift circuit. It is disposed in a feedback part and used as a constant current source in a logic circuit comprising a logic part consisting of a differential transistor circuit and the feedback part for negatively feeding back the in-phase output of the differential transistor circuit.

    摘要翻译： 本发明的晶体管电路包括用于在其基极处接收第一偏压的第一晶体管，连接到第一晶体管的集电极的电阻器件和连接到第一晶体管和电阻器装置之间的结的钳位装置， 电阻器的端子与其与第一晶体管的连接相对。 当在第一晶体管中产生由于α射线引起的噪声电流并且输出降低时，钳位装置以使得电流流过钳位装置并防止输出变化的方式工作。 本发明的晶体管电路连接到电阻器或晶体管，并作为恒流电路用于向电阻器或晶体管提供电流，使得流过其中的电流恒定。 例如，它被用作射极跟随器的恒流源来构成电平移位电路。 它被布置在反馈部分中，并在逻辑电路中用作恒流源，该逻辑电路包括由差分晶体管电路和反馈部分组成的逻辑部分，用于对差分晶体管电路的同相输出进行负反馈。

    Flip-flop circuit
    9.
    发明授权
    Flip-flop circuit 失效
    触发电路

    公开(公告)号：US4868420A

    公开(公告)日：1989-09-19

    申请号：US273729

    申请日：1988-11-18

    申请人： Hiroyuki Itoh ,  Masayoshi Yagyu ,  Toshio Yamada ,  Masaru Osanai ,  Akira Masaki ,  Mitsuo Usami ,  Tohru Kobayashi ,  Masato Hamamoto

    发明人： Hiroyuki Itoh ,  Masayoshi Yagyu ,  Toshio Yamada ,  Masaru Osanai ,  Akira Masaki ,  Mitsuo Usami ,  Tohru Kobayashi ,  Masato Hamamoto

    IPC分类号： H03K3/037 ,  H03K3/2885

    CPC分类号： H03K3/2885 ,  H03K3/0375

    摘要： An improved flip-flop circuit is provided which prevents the occurrence of soft errors due to .alpha. rays and the like emitted from a trace amount of radioactive materials contained in a semiconductor package material. The flip-flop circuit has a first logic circuit which holds data and produces a first logic signal and a second logic circuit which produces a second logic signal. A logic gate receives the first and second logic signals that are produced from the first and second logic circuits and which have the same logic level. The output of the logic gate is input to the first logic circuit through a feedback loop which is provided between the output and the input of the first logic circuit and which includes the logic gate. According to the circuit construction of the present invention, a flip-flop circuit can be accomplished which is resistant to the radioactive rays such as .alpha. rays and does not cause soft errors.

    摘要翻译： 提供一种改进的触发器电路，其防止由包含在半导体封装材料中的痕量放射性材料发射的α射线等引起的软误差的发生。 触发器电路具有保持数据并产生第一逻辑信号的第一逻辑电路和产生第二逻辑信号的第二逻辑电路。 逻辑门接收从第一和第二逻辑电路产生并具有相同逻辑电平的第一和第二逻辑信号。 逻辑门的输出通过反馈回路输入到第一逻辑电路，反馈回路设置在第一逻辑电路的输出端和输入端之间，并包括逻辑门。 根据本发明的电路结构，可以实现对诸如α射线的放射线的耐受性并且不引起软错误的触发器电路。