公开(公告)号：US08554982B2

公开(公告)日：2013-10-08

申请号：US11251867

申请日：2005-10-18

申请人： Toshiyuki Nishihara ,  Yoshio Sakai

发明人： Toshiyuki Nishihara ,  Yoshio Sakai

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0246 ,  G06F3/0641 ,  G06F12/00 ,  G06F12/0223 ,  G06F12/08 ,  G06F12/0813 ,  G06F12/0866 ,  G06F12/10 ,  G06F12/1009 ,  G06F12/1081 ,  G06F13/28 ,  G06F2212/1024 ,  G06F2212/2022 ,  G06F2212/2024 ,  G06F2212/7201 ,  G11C8/08 ,  G11C11/22 ,  Y02D10/13

摘要： A storage device able to make a redundant write operation of unselected data unnecessary and able to optimize an arrangement of pages to a state having a high efficiency for rewriting, wherein the storage device has a first memory unit, a second memory unit having a different access speed from the first memory, and a control circuit, wherein the control circuit has a function of timely moving the stored data in two ways between the first memory unit and the second memory unit having different access speeds in reading or rewriting.

摘要翻译： 一种存储装置，其能够对未选择的数据进行冗余写入操作，并且能够将页面的布置优化为具有用于重写的高效率的状态，其中所述存储装置具有第一存储器单元，具有不同访问的第二存储器单元 第一存储器的速度以及控制电路，其中控制电路具有在读取或重写中具有不同访问速度的第一存储器单元和第二存储器单元之间以两种方式及时移动存储的数据的功能。

公开(公告)号：US07596453B2

公开(公告)日：2009-09-29

申请号：US11878840

申请日：2007-07-27

申请人： Yoshio Sakai

发明人： Yoshio Sakai

IPC分类号： G06F19/00 ,  G06F15/00

CPC分类号： G01G19/44 ,  G01G23/10

摘要： A digital scale is provided that switches a measuring interval according to the amount of variation of sampled data, and computes a weight. Embodiments include a scale with pre-stored scale intervals set at multiple levels, and allowable ranges of fluctuation that correspond to the scale intervals. The scale acquires digital data of a load continuously, and computes a predetermined number, or a fluctuation range in a predetermined time, of the acquired digital data. The scale then determines the degree of variation of the digital data by comparing the computed fluctuation range with the allowable range of fluctuation stored for each scale interval, and switches the scale interval based on the determined degree of variation, thereby allowing the scale to measure and compute the weight of the load even if the fluctuation is large.

摘要翻译： 提供数字刻度，根据采样数据的变化量切换测量间隔，并计算重量。 实施例包括具有设置在多个级别上的预先存储的刻度间隔的刻度，以及对应于刻度间隔的允许的波动范围。 该刻度尺持续地获取负载的数字数据，并计算所获取的数字数据的预定数量或预定时间的波动范围。 然后，通过将计算出的波动范围与每个刻度间隔所存储的波动允许范围进行比较来确定数字数据的变化程度，并根据确定的变化程度切换刻度间隔，从而允许刻度测量和 即使波动较大，也可以计算负载的重量。

公开(公告)号：US07466915B2

公开(公告)日：2008-12-16

申请号：US11038056

申请日：2005-01-21

申请人： Yuji Ishii ,  Kazuyuki Mori ,  Tamotsu Akashi ,  Yoshio Sakai

发明人： Yuji Ishii ,  Kazuyuki Mori ,  Tamotsu Akashi ,  Yoshio Sakai

IPC分类号： H04J14/00 ,  H04B10/00

CPC分类号： G02B6/3588 ,  G02B6/3512 ,  G02B6/3556 ,  H04Q11/0005 ,  H04Q2011/003 ,  H04Q2011/0039 ,  H04Q2011/0043

摘要： A mirror controller of an optical switch comprises a signal generator (10, 82, 83) for passing the optical signal on the same light path as the one for optical communication using the optical switch, and an image analyzer (15, 16, 81) detecting the optical signal as the light scattered by at least one of tilt mirrors (111, 123) and an output collimator array (14). The image analyzer detects the position of the light beam image as a control position (121, 141, 85) based on the scattered light, and controls the tilt mirrors in such a manner that the detected control position coincides with the predetermined desired target position (122, 142, 84, 86) on at least one of the tilt mirrors and the output collimator array. The mirror controller can realize the connection test of the optical signal between input and output with high accuracy and reliability.

摘要翻译： 一种光开关的镜面控制器包括：信号发生器（10,82,83），用于使光信号与用于使用光开关的光通信相同的光路通过;以及图像分析器（15,16,81） 检测作为由倾斜镜（111,123）和输出准直器阵列（14）中的至少一个散射的光的光信号。 图像分析仪基于散射光检测光束图像的位置作为控制位置（121,141,85），并且以这样的方式控制倾斜镜，使得检测到的控制位置与预定的期望目标位置（ 122,142,84,86）在至少一个倾斜镜和输出准直器阵列上。 镜面控制器可以高精度，高可靠性实现输入和输出之间光信号的连接测试。

公开(公告)号：US07440649B2

公开(公告)日：2008-10-21

申请号：US11652041

申请日：2007-01-11

申请人： Yoshio Sakai ,  Kazuyuki Mori ,  Satoshi Ide

发明人： Yoshio Sakai ,  Kazuyuki Mori ,  Satoshi Ide

IPC分类号： G02B6/26 ,  G02B6/42

CPC分类号： H04Q11/0005 ,  G02B6/3512 ,  G02B6/356 ,  G02B6/359 ,  H04Q2011/003 ,  H04Q2011/0039 ,  H04Q2011/0043 ,  H04Q2011/0049 ,  H04Q2011/0083

摘要： A wavelength selective switch module is disclosed. The wavelength selective switch module includes: a unit for generating test light; a multiplexing unit for multiplexing the test light with the wavelength multiplexed light; a splitting unit for splitting the test light from output light of each of two output ports; a feedback control unit for obtaining deflection control amounts for the deflection unit corresponding to a wavelength of the test light such that a light level of the test light that is split from the output light output from each of the two output ports becomes maximum; and a calculation unit for calculating deflection control amounts for output ports other than the two output ports for the deflection unit for the test light and calculating deflection control amounts for output ports for deflection units of wavelengths included in the wavelength multiplexed light using the deflection control amounts for the deflection unit for the test light output from each of the two output ports by which the light level of the test light becomes maximum.

公开(公告)号：US20080050064A1

公开(公告)日：2008-02-28

申请号：US11591590

申请日：2006-11-02

申请人： Yoshio Sakai ,  Kazuyuki Mori

发明人： Yoshio Sakai ,  Kazuyuki Mori

IPC分类号： G02B6/26

CPC分类号： H04Q11/0005 ,  G02B6/3512 ,  G02B6/3556 ,  G02B6/359 ,  H04Q2011/003 ,  H04Q2011/0039 ,  H04Q2011/0049 ,  H04Q2011/0083

摘要： A MEMS optical switch device is disclosed that includes an optical system deflecting and outputting light signals; first and second test light generation parts generating and feeding first and second test lights to specific input and output ports, respectively, of the optical system; first and second divergence parts diverging the first and second test lights, respectively, from the optical system; first and second monitoring parts detecting the diverged first and second test lights, respectively; and an operational check part causing the first and second test lights to be incident on output and input deflection parts of the optical system by driving a specific input deflection part corresponding to the specific input port and a specific output deflection part corresponding to the specific output port, respectively, and performing an operational check on the output and input deflection parts from the light levels of the detected first and second test lights, respectively.

摘要翻译： 公开了一种MEMS光开关装置，其包括偏转和输出光信号的光学系统; 第一和第二测试光产生部件分别产生并将第一和第二测试光馈送到光学系统的特定输入和输出端口; 第一和第二发散部分别从第一和第二测试光分离光学系统; 分别检测发散的第一和第二测试灯的第一和第二监视部分; 以及操作检查部，通过驱动对应于特定输入端口的特定输入偏转部分和对应于特定输出端口的特定输出偏转部分，使第一和第二测试光入射到光学系统的输出和输入偏转部分 并且分别从检测到的第一和第二测试灯的光级别对输出和输入偏转部分进行操作检查。

公开(公告)号：US07303927B2

公开(公告)日：2007-12-04

申请号：US10834547

申请日：2004-04-29

申请人： Chiharu Isobe ,  Yoshio Sakai

发明人： Chiharu Isobe ,  Yoshio Sakai

IPC分类号： H01L21/20

CPC分类号： H01L28/55 ,  H01L27/11502 ,  H01L27/11507

摘要： A ferroelectric capacitor is provided in which the surface area of a ferroelectric thin film is expanded to increase the amount of polarization. In the ferroelectric capacitor, hemi-spherical protruding parts 31 are formed with HSG-growth on the surface of a polycrystalline silicon film 30. On the polycrystalline silicon film 30 having the hemi-spherical protruding parts 31 are sequentially laminated an adhesive layer 32, lower electrode 33, ferroelectric film 34, and upper electrode 35. The ferroelectric film 34 is shaped to overlap the shape of hemi-spherical protruding parts 31 of the polycrystalline silicon film 30, and the surface area thereof is expanded.

摘要翻译： 提供了强电介质电容器，其中铁电薄膜的表面积被扩大以增加极化量。 在铁电电容器中，半球状突出部31在多晶硅膜30的表面上形成有HSG生长。在具有半球状突出部31的多晶硅膜30上依次层叠有粘合剂层32，下部 电极33，铁电体膜34和上部电极35.铁电体膜34成形为与多晶硅膜30的半球形突出部31的形状重叠，其表面积扩大。

公开(公告)号：US20070165468A1

公开(公告)日：2007-07-19

申请号：US11716710

申请日：2007-03-12

申请人： Toshiyuki Nishihara ,  Yoshio Sakai

发明人： Toshiyuki Nishihara ,  Yoshio Sakai

IPC分类号： G11C29/00 ,  G11C7/00

CPC分类号： G11C29/4401 ,  G11C29/44 ,  G11C29/846 ,  G11C2029/1208

摘要： A semiconductor memory device enabling efficient repair of defects by using limited redundant memory while suppressing a drop of access speed accompanied with the repair of defects of the memory, wherein a first memory array is divided into a plurality of memory regions for each 16 word lines and wherein defective memory addresses in regions are stored in a second memory array. When a memory address for accessing the first memory array is input, the defective memory address of the memory region including the memory to be accessed is read out from the second memory array. In this way, the addresses of defective memory in 16 word lines worth of a memory region are stored in the second memory array 2, therefore addresses of a wider range of defective memory can be stored. For this reason, it becomes possible to repair defects occurring at random efficiently.

摘要翻译： 一种半导体存储器件，其能够通过使用有限的冗余存储器来有效地修复缺陷，同时抑制伴随着存储器的缺陷的修复的存取速度的下降，其中第一存储器阵列被分成用于每16个字线的多个存储区域， 其中区域中的有缺陷的存储器地址存储在第二存储器阵列中。 当输入用于访问第一存储器阵列的存储器地址时，从第二存储器阵列读出包括要访问的存储器的存储器区域的缺陷存储器地址。 以这种方式，存储在存储器区域中的16个字线的缺陷存储器的地址被存储在第二存储器阵列2中，因此可以存储更宽范围的有缺陷的存储器的地址。 为此，可以有效地修复随机发生的缺陷。

公开(公告)号：US20060047212A1

公开(公告)日：2006-03-02

申请号：US11212565

申请日：2005-08-29

申请人： Daming Wei ,  Yoshio Sakai

发明人： Daming Wei ,  Yoshio Sakai

IPC分类号： A61B5/0402

CPC分类号： A61B5/04028 ,  A61B5/0402 ,  A61B5/0428

摘要： Four first electrodes are attached on the vicinity of a lower right end of a right clavicle, the vicinity of a lower left end of a left clavicle, the vicinity of a position on a right anterior axillary line at the level of a right lowermost rib, a the vicinity of a position on a left anterior axillary line at the level of a left lowermost rib of a living body, so as to correspond to limb leads of a standard 12-lead electrocardiogram (ECG). Two second electrodes are attached on such positions of the living body that correspond to a lead V2 and a lead V4 of chest leads of the standard 12-lead ECG. A first ECG data set corresponding to leads I and II of the standard 12-lead EGG with the first electrodes. A second ECG data set including the leads V2 and V4 with the second electrodes. An instantaneous electromotive force vector (a heart vector) is calculated based on the first and second ECG data sets, and predetermined first lead vectors of the leads I, II, V2 and V4. A third ECG data set including leads V1, V3, V5 and V6 of the chest leads is calculated based on the heart vector-and predetermined second lead vectors of the leads V1, V3, V5 and V6. A fourth EGG data set corresponding to leads III, aVR, aVL and aVF of the standard 12-lead EGG based on the first ECG data set The standard 12-lead EGG is derived based on the first to fourth ECG data sets.

摘要翻译： 四个第一电极附着在右锁骨的右下端附近，左锁骨左下端附近，右下腋下线位于右下肋骨附近， 在生物体的左下肋骨的水平处的左前腋细线上的位置附近，以与标准12导联心电图（ECG）的肢体引线相对应。 两个第二电极附接在对应于标准12导联ECG的胸部引线的引线V 2和引线V 4的生物体的这些位置上。 对应于具有第一电极的标准12导联EGG的引线I和II的第一ECG数据集。 包括具有第二电极的引线V 2和V 4的第二ECG数据集。 基于第一和第二ECG数据集以及引线I，II，V 2和V 4的预定的第一引导向量来计算瞬时电动势矢量（心脏矢量）。 基于引线V 1，V 3，V 5和V 6的心脏矢量和预定的第二引导矢量计算包括胸部引线的引线V 1，V 3，V 5和V 6的第三ECG数据集。 基于第一ECG数据集的与标准12导联EGG的引线III，aVR，aVL和aVF相对应的第四个EGG数据集。基于第一至第四ECG数据集导出标准的12引导EGG。

公开(公告)号：US5699807A

公开(公告)日：1997-12-23

申请号：US507709

申请日：1995-07-26

申请人： Jun Motogi ,  Yoshio Sakai ,  Sunao Takeda

发明人： Jun Motogi ,  Yoshio Sakai ,  Sunao Takeda

IPC分类号： A61B5/022 ,  A61B5/02

CPC分类号： A61B5/02116 ,  A61B5/022 ,  A61B5/7239

摘要： A pressure sensor gathers discrete data representing the pulse amplitude of a pulse wave signal when a cuff pressure is increased and decreased. A RAM stores the discrete data of the pulse amplitude. A CPU processes the discrete data by using a spline function, to thereby generate the data representative of a smooth continuous line passing by points of the pulse amplitude of the discrete data. This process reduces a variation of the pulse amplitude of a pulse wave signal, to thereby minimize a variation of the blood pressure values. An inflection point of the smooth continuous line is used as a diastolic blood pressure value.

摘要翻译： 当袖带压力增加和减小时，压力传感器收集表示脉搏波信号的脉冲幅度的离散数据。 RAM存储脉冲幅度的离散数据。 CPU通过使用样条函数处理离散数据，从而生成表示通过离散数据的脉冲幅度的点的平滑连续线的数据。 该过程减少了脉搏波信号的脉冲幅度的变化，从而使血压值的变化最小化。 平滑连续线的拐点被用作舒张血压值。

公开(公告)号：US5646423A

公开(公告)日：1997-07-08

申请号：US470451

申请日：1995-06-06

申请人： Satoshi Meguro ,  Kiyofumi Uchibori ,  Norio Suzuki ,  Makoto Motoyoshi ,  Atsuyoshi Koike ,  Toshiaki Yamanaka ,  Yoshio Sakai ,  Toru Kaga ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Shigeru Honjou ,  Osamu Minato

发明人： Satoshi Meguro ,  Kiyofumi Uchibori ,  Norio Suzuki ,  Makoto Motoyoshi ,  Atsuyoshi Koike ,  Toshiaki Yamanaka ,  Yoshio Sakai ,  Toru Kaga ,  Naotaka Hashimoto ,  Takashi Hashimoto ,  Shigeru Honjou ,  Osamu Minato

IPC分类号： H01L21/8244 ,  H01L27/11 ,  H01L29/04 ,  H01L31/036

CPC分类号： H01L27/1104 ,  H01L27/11 ,  H01L27/1108 ,  Y10S257/903 ,  Y10S257/904

摘要： A memory cell of the type a pair of cross-coupled CMOS inverters of a SRAM is disclosed in which the load MISFETs are stacked above the semiconductor substrate and over the drive MISFETS. Each load MISFET of a memory cell consists of a source, drain and channel region formed within the same polycrystalline silicon film, and a gate electrode consisting of a different layer conductive film than that of the drive MISFETs. In a memory cell having such a stacked arrangement, the source (drain) region and gate electrode of each load MISFET thereof are patterned to have an overlapping relationship with each other so as to increase the effective capacitance associated with each of the memory cell storage nodes. The gate electrodes of both the drive and load MISFETs are formed of n-type and p-type polycrystalline silicon films, respectively, and the drain regions of the first and second p-channel load MISFETs are electrically connected to the drain regions of the first and second n-channel drive MISFETs through separate polycrystalline silicon films, respectively. The polycrystalline silicon gate electrodes of the first and second load MISFETs are respectively electrically connected to the drain regions of the second and first drive MISFETs in each memory cell of the SRAM, furthermore.

摘要翻译： 公开了SRAM的一对交叉耦合CMOS反相器的类型的存储单元，其中负载MISFET堆叠在半导体衬底之上和驱动MISFETS之上。 存储单元的每个负载MISFET由形成在同一多晶硅膜内的源极，漏极和沟道区域以及由与驱动MISFET不同的导电膜构成的栅电极组成。 在具有这种堆叠布置的存储单元中，其每个负载MISFET的源极（漏极）区域和栅电极被图案化以具有彼此重叠的关系，从而增加与每个存储单元存储节点相关联的有效电容 。 驱动和负载MISFET两者的栅电极分别由n型和p型多晶硅膜形成，并且第一和第二p沟道负载MISFET的漏极区域电连接到第一 和第二n沟道驱动MISFET分别通过单独的多晶硅膜。 此外，第一和第二负载MISFET的多晶硅栅电极分别电连接到SRAM的每个存储单元中的第二和第一驱动MISFET的漏极区。