Abstract:
Various embodiments are disclosed relating to wireless receivers. According to an example embodiment, a method and apparatus are provided. The method may include receiving an input signal within a first frequency range (e.g., RF). The input signal may include a desired signal and a blocker signal. The method may also include down-converting the input signal to a second frequency range (e.g., IF) that is lower than the first frequency range, separating the blocker signal from desired signal (e.g., at the second frequency range), up-converting the separated blocker signal to the first frequency range (e.g., RF), and subtracting the up-converted blocker signal from the input signal.
Abstract:
Low flicker noise mixer and buffer. This design employs some native metal oxide semiconductor field-effect transistors (MOSFETs) (e.g., having no threshold voltage) within a passive mixer whose gates are driven using clock signals. These native MOSFETs maybe biased at one half of the power supply voltage to provide a lower noise figure. A cooperatively operating buffer employs appropriately places MOSFETs and resistors to ensure the desired gain. Relatively larger valued resistors can be employed to provide for higher voltage gain, and this can sometimes be accompanied with using a higher than typical power supply voltage. Source followers serve as output buffers and also ensure the required output DC voltage level as well. It is also noted that this design can be implemented using n-channel metal oxide semiconductor field-effect transistors (N-MOSFETs) of p-channel metal oxide semiconductor field-effect transistors (P-MOSFETs).
Abstract:
An RF front-end includes a receiver frequency band filter module, a low noise amplifier, a first power amplifier module, a second power amplifier module, and a transmit frequency band filter module. The receiver frequency band filter module filters a received RF signal and the low noise amplifier amplifies the signal in accordance with the first or the second RF front-end configuration signal. The first power amplifier module is enabled in accordance with the first RF front-end configuration signal to amplify the first outbound RF signal and the second power amplifier module is enabled in accordance with the second RF front-end configuration signal to amplify the second outbound RF signal. The transmitter frequency band filter module is enabled in accordance with the second RF front-end configuration signal to filter the second transmit RF signal.
Abstract:
A method and apparatus for dynamically controlling a programmable gain amplifier (PGA) to provide a plurality of gain steps thereby providing automatic gain control (AGC) in a receiver intermediate frequency (IF) stage comprising a succession of operational amplifiers wherein at least one is for providing fine gain control and wherein the gain of each fine gain amplifier is controlled by the resistance ratios of a plurality of selectively biased MOSFETs. In one embodiment of the invention, three coarse amplifiers are provided, each having a gain of either 0 dB or 12 dB based on the value of a two-state signal provided to each amplifier gain control input. A single fine gain amplifier has a gain of 0 dB, 3 dB, 6 dB or 9 dB based on the binary value of the two-bit signal provided to the amplifier.
Abstract:
An RFIC includes first and second RF sections, first and second PHY processing modules, first and second upper layer processing modules, and memory. When the RFIC is in a first receive mode, the first RF section, the first PHY processing module, and the first upper layers processing module convert a first inbound RF signal into a first inbound audio signal in accordance with a first wireless communication protocol. When the RFIC is in a second receive mode, the second RF section, the second PHY processing module, and the second upper layers processing module convert a second inbound RF signal into a second inbound audio signal in accordance with a second wireless communication protocol. The memory stores the first and second inbound audio signals. The first PHY processing module retrieves, based on the receive mode, the first or second inbound audio signal from the memory and converts the first or second inbound audio signal into a first or second inbound analog audio signal.
Abstract:
A highly linear and very low-noise down-conversion mixer for extracting weak signals in the presence of very strong unwanted signals is disclosed. Aspects of an embodiment may include a source follower circuit in a transmitter front end of a mobile terminal. The source follower circuit may receive RF signals prior to the RF signals being amplified by a power amplifier for transmission. The RF signals may comprise in-phase and quadrature components. The source follower circuit may generate output RF voltage signals, and communicate the output RF voltage signals to a switching circuit via a coupling capacitor. The switching circuit may down-convert the communicated output RF voltage signals to generate differential baseband signals. The capacitance of the coupling capacitor may be changed to change gain and/or linearity of the differential baseband signals. Each of the differential baseband signals may be low-pass filtered to attenuate higher frequencies.
Abstract:
According to one exemplary embodiment, a transceiver for nullification of a noise component in a transmitter comprises a noise nullification module loading a selected node in the transmitter. The noise nullification module comprises a mixer that receives inputs from the selected node and a local oscillator, where the mixer is also coupled to a filter such that the noise nullification module presents a low impedance at an approximate frequency of a noise component so as to nullify the noise component. In one embodiment, the noise nullification module results in band-pass filtering of an approximate receive signal frequency so as to nullify a noise component at the receive frequency. In another embodiment, the noise nullification module results in notch filtering of an approximate transmit signal frequency so as to nullify a noise component at a receive signal frequency.
Abstract:
A digital to analog conversion (DAC) module includes a digital to analog converter, a sample and hold circuit, and a switch module. The digital to analog converter is coupled to convert a digital signal into an analog signal. The sample and hold circuit is coupled to sample the analog signal to produce a sampled analog signal. The switch module is coupled to provide the analog signal as an output of the DAC module when the DAC module in a first mode and to output the analog signal to the sample and hold circuit when the DAC module in a second mode, wherein the sampled analog signal provides the output of the DAC module in the second mode.
Abstract:
A bias filtering module with at least two capacitive levels satisfies both a settle time requirement and a filtering requirement using a voltage dependent filter module whose capacitance is a function of a voltage potential on the filtering circuitry output terminal. The final capacitance level is approximately three times larger than the initial capacitance level. MOS capacitors having a voltage dependent charge capacity within the bias filtering module are coupled between a plurality of bias lines and circuit common. In an alternate embodiment, a selectable first group of capacitors are switched into connection within the bias filtering module as a second group of capacitors approximately reach a fully charged state within a specified settle time to provide improved filtering.
Abstract:
A polar transmitter includes a digital processor for producing a phase correction signal and a complex modulated digital signal including a digital phase-modulated signal. The phase correction signal is added to the digital phase-modulated signal to produce a corrected digital phase signal. The corrected digital phase signal is input to a phase-locked loop (PLL) to produce an RF phase signal that tracks the phase of the digital phase-modulated signal based on the corrected digital phase signal.