公开(公告)号：US08173498B2

公开(公告)日：2012-05-08

申请号：US12623497

申请日：2009-11-23

Applicant: Hsiang-Lin Lin ,  Ching-Huan Lin ,  Chih-Hung Shih ,  Wei-Ming Huang

Inventor： Hsiang-Lin Lin ,  Ching-Huan Lin ,  Chih-Hung Shih ,  Wei-Ming Huang

IPC: H01L21/00 ,  H01L21/84

CPC classification number: H01L27/124

Abstract: A method for manufacturing an array substrate is provided, wherein a data line is composed of first and second segments connected by a contact pad. First and second insulation layers are disposed between the first segment of the data line and a shielding electrode. In addition, the first insulation layer is disposed between the second segment of the data line and a gate line in their overlapping area. Accordingly, the coupling effect between the conductive layers can be reduced. For example, the RC delay problem due to parasitic capacitance between the shielding electrode and the data line is solved. As a result of the design of the two insulator layers between the first segment of the data line and the shielding electrode, the shorting between the conductive layers can also be simultaneously solved and the product yield can be increased.

Abstract translation: 提供一种阵列基板的制造方法，其中数据线由通过接触焊盘连接的第一和第二段构成。 第一和第二绝缘层设置在数据线的第一段和屏蔽电极之间。 此外，第一绝缘层设置在数据线的第二段和其重叠区域中的栅极线之间。 因此，可以降低导电层之间的耦合效应。 例如，解决了由于屏蔽电极和数据线之间的寄生电容引起的RC延迟问题。 作为数据线的第一段与屏蔽电极之间的两个绝缘体层的设计的结果，导电层之间的短路也可以同时解决，并且可以提高产品的产率。

公开(公告)号：US08064001B2

公开(公告)日：2011-11-22

申请号：US12419305

申请日：2009-04-07

Applicant: Sung-Kao Liu ,  Hsiang-Lin Lin ,  Ching-Huan Lin ,  Chih-Jen Hu

Inventor： Sung-Kao Liu ,  Hsiang-Lin Lin ,  Ching-Huan Lin ,  Chih-Jen Hu

IPC: G02F1/133 ,  G02F1/1337 ,  G09G3/36

CPC classification number: G02F1/1393 ,  G02F1/133753 ,  G02F1/134309 ,  G02F1/134363 ,  G02F2001/134381 ,  G02F2201/122

Abstract: A pixel structure includes at least a pixel electrode, and at least an aligning electrode. The pixel electrode, which has a central opening, is disposed on a substrate. The aligning electrode, which is disposed between the pixel electrode and substrate, includes an aligning part disposed under and corresponding to the central part of the pixel electrode. The aligning voltage applied to the aligning electrode is greater than the pixel voltage applied to the pixel electrode.

Abstract translation: 像素结构至少包括像素电极和至少一个对准电极。 具有中心开口的像素电极设置在基板上。 设置在像素电极和基板之间的对准电极包括设置在像素电极的中心部分下方并对应于其的中心部分的对准部。 施加到对准电极的取向电压大于施加到像素电极的像素电压。

公开(公告)号：US20110216055A1

公开(公告)日：2011-09-08

申请号：US12861851

申请日：2010-08-24

Applicant: Chung-Hsiang Chiu ,  Hsiang-Lin Lin ,  Chung-Yi Chang ,  Sheng-Wen Huang ,  Chih-Jen Hu

Inventor： Chung-Hsiang Chiu ,  Hsiang-Lin Lin ,  Chung-Yi Chang ,  Sheng-Wen Huang ,  Chih-Jen Hu

IPC: G09G5/00 ,  G09G3/34

CPC classification number: G09G5/00 ,  G09G3/34

Abstract: A method of driving an electrophoretic display is set forth for avoiding image-edge residual while sequentially displaying a first frame and a second frame. During the time of displaying the first frame, set a common voltage to be a first voltage, apply a second voltage different from the first voltage to a first pixel for writing a first data signal into the first pixel, and apply the first voltage to a second pixel adjacent to the first pixel for retaining a second data signal of the second pixel, which is different from the first data signal. During the time of displaying the second frame, set the common voltage to be the second voltage, apply the first voltage to the first pixel for writing the second data signal into the first pixel, and apply the first voltage to the second pixel for retaining the second data signal of the second pixel.

Abstract translation: 阐述了驱动电泳显示器的方法，以便在顺序地显示第一帧和第二帧的同时避免图像边缘残差。 在显示第一帧的时间期间，将公共电压设置为第一电压，将不同于第一电压的第二电压施加到第一像素，以将第一数据信号写入第一像素，并将第一电压施加到 与第一像素相邻的第二像素，用于保持与第一数据信号不同的第二像素的第二数据信号。 在显示第二帧期间，将公共电压设置为第二电压，将第一电压施加到第一像素，以将第二数据信号写入第一像素，并将第一电压施加到第二像素，以保持第 第二像素的第二数据信号。

公开(公告)号：US07951629B2

公开(公告)日：2011-05-31

申请号：US12704537

申请日：2010-02-12

Applicant: Hsiang-Lin Lin ,  Sung-Kao Liu

Inventor： Hsiang-Lin Lin ,  Sung-Kao Liu

IPC: H01L21/00

CPC classification number: G02F1/136227 ,  G02F1/136213 ,  G02F2001/13606 ,  G02F2001/136218

Abstract: A method of manufacturing a pixel structure is provided. A first patterned conductive layer including a gate and a data line is formed on a substrate. A gate insulating layer is formed to cover the first patterned conductive layer and a semiconductor channel layer is formed on the gate insulating layer above the gate. A second patterned conductive layer including a scan line, a common line, a source and a drain is formed on the gate insulating layer and the semiconductor channel layer. The scan line is connected to the gate and the common line is located above the data line. The source and drain are located on the semiconductor channel layer, and the source is connected to the data line. A passivation layer is formed on the substrate to cover the second patterned conductive layer. A pixel electrode connected to the drain is formed on the passivation layer.

Abstract translation: 提供了一种制造像素结构的方法。 在基板上形成包括栅极和数据线的第一图案化导电层。 形成栅极绝缘层以覆盖第一图案化导电层，并且在栅极上方的栅极绝缘层上形成半导体沟道层。 包括扫描线，公共线，源极和漏极的第二图案化导电层形成在栅极绝缘层和半导体沟道层上。 扫描线连接到栅极，公共线位于数据线上方。 源极和漏极位于半导体沟道层上，源极连接到数据线。 在衬底上形成钝化层以覆盖第二图案化导电层。 连接到漏极的像素电极形成在钝化层上。

公开(公告)号：US20100315583A1

公开(公告)日：2010-12-16

申请号：US12788876

申请日：2010-05-27

Applicant: Hsiang-Lin Lin ,  Ching-Huan Lin ,  Chih-Hung Shih ,  Wei-Ming Huang ,  Chih-Hung Lin ,  Yu-Cheng Chen ,  Yi-Hui Li ,  Tsan-Chun Wang

Inventor： Hsiang-Lin Lin ,  Ching-Huan Lin ,  Chih-Hung Shih ,  Wei-Ming Huang ,  Chih-Hung Lin ,  Yu-Cheng Chen ,  Yi-Hui Li ,  Tsan-Chun Wang

IPC: G02F1/1343 ,  H01L21/84

CPC classification number: G02F1/136209 ,  G02F1/136213 ,  G02F2001/13606 ,  G02F2201/40 ,  H01L27/1248 ,  H01L27/1255

Abstract: This invention in one aspect relates to a pixel structure. In one embodiment, the pixel structure includes a scan line formed on a substrate and a data line formed over the substrate defining a pixel area, a switch formed inside the pixel area on the substrate, a shielding electrode formed over the switch, a plane organic layer formed over the date line and the pixel area and having no overlapping with the shielding electrode, and a pixel electrode having a first portion and a second portion extending from the first portion, and formed over the shielding electrode and the plane organic layer in the pixel area, wherein the first portion is overlapped with the shielding electrode so as to define a storage capacitor therebetween, and the second portion overlays the plane organic layer and has no overlapping with the data line.

Abstract translation: 本发明在一个方面涉及像素结构。 在一个实施例中，像素结构包括形成在衬底上的扫描线和形成在限定像素区域的衬底上的数据线，形成在衬底上的像素区域内的开关，形成在开关上的屏蔽电极，有机平面 形成在日期线和像素区域上并且与屏蔽电极不重叠的像素电极，以及具有从第一部分延伸的第一部分和第二部分的像素电极，并且形成在屏蔽电极和平面有机层的上方 像素区域，其中第一部分与屏蔽电极重叠以便在其间限定存储电容器，并且第二部分覆盖平面有机层并且不与数据线重叠。

公开(公告)号：US20100213464A1

公开(公告)日：2010-08-26

申请号：US12775493

申请日：2010-05-07

Applicant: Wei-Sheng Yu ,  Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Hsien-Chieh Tseng ,  Han-Tu Lin

Inventor： Wei-Sheng Yu ,  Kuo-Lung Fang ,  Hsiang-Lin Lin ,  Hsien-Chieh Tseng ,  Han-Tu Lin

IPC: H01L33/16

CPC classification number: H01L27/124 ,  H01L27/1248 ,  H01L27/1288

Abstract: An active matrix array structure, disposed on a substrate, includes a first patterned conductive layer, a patterned gate insulating layer, a patterned semiconductor layer, a second patterned conductive layer, a patterned overcoat layer and a transparent conductive layer. The patterned gate insulating layer has first openings that expose a part of the first patterned conductive layer. The patterned semiconductor layer is disposed on the patterned gate insulating layer. The second patterned conductive layer is disposed on the patterned semiconductor layer. The patterned overcoat layer has second openings that expose a part of the first patterned conductive layer and a part of the second patterned conductive layer. The transparent conductive layer is completely disposed on the substrate. The transparent conductive layer disposed in the first openings and the second openings is broken off at a position that is in between the substrate and the patterned overcoat layer.

Abstract translation: 设置在基板上的有源矩阵阵列结构包括第一图案化导电层，图案化栅极绝缘层，图案化半导体层，第二图案化导电层，图案化外涂层和透明导电层。 图案化栅极绝缘层具有暴露第一图案化导电层的一部分的第一开口。 图案化的半导体层设置在图案化的栅极绝缘层上。 第二图案化导电层设置在图案化的半导体层上。 图案化的外涂层具有暴露第一图案化导电层的一部分和第二图案化导电层的一部分的第二开口。 透明导电层完全设置在基板上。 设置在第一开口和第二开口中的透明导电层在基板和图案化外涂层之间的位置处断开。

公开(公告)号：US20100193827A1

公开(公告)日：2010-08-05

申请号：US12507935

申请日：2009-07-23

Applicant: Hsiang-Lin Lin

Inventor： Hsiang-Lin Lin

IPC: H01L33/00

CPC classification number: H01L27/12 ,  H01L27/124 ,  H01L27/1248

Abstract: A pixel structure includes a first patterned metal layer, a gate insulating layer, a semiconductor channel layer, a second patterned metal layer, a passivation layer, and a conducting layer. A gate line of the second patterned metal layer is electrically connected by the conducting layer to a gate extension electrode of the first patterned metal layer. A source electrode of the second patterned metal layer is electrically connected by the conducting layer to a second data line segment of the first patterned metal layer. A method for fabricating a pixel structure is also disclosed herein.

Abstract translation: 像素结构包括第一图案化金属层，栅极绝缘层，半导体沟道层，第二图案化金属层，钝化层和导电层。 第二图案化金属层的栅极线通过导电层电连接到第一图案化金属层的栅极延伸电极。 第二图案化金属层的源电极通过导电层电连接到第一图案化金属层的第二数据线段。 本文还公开了一种用于制造像素结构的方法。

公开(公告)号：US20100187531A1

公开(公告)日：2010-07-29

申请号：US12725458

申请日：2010-03-17

Applicant: Hsiang-Lin Lin ,  Chun-Chieh Tsao

Inventor： Hsiang-Lin Lin ,  Chun-Chieh Tsao

IPC: H01L33/16

CPC classification number: G02F1/133555 ,  G02F1/136227 ,  H01L27/124 ,  H01L27/1248

Abstract: A pixel structure including a gate, a gate dielectric layer, a patterned semiconductor layer having a channel area disposed above the gate, a patterned dielectric layer having an etching-stop layer disposed above the gate and a number of bumps, a patterned metal layer having a reflective pixel electrode, a source and a drain, an overcoat dielectric layer, and a transparent pixel electrode sequentially disposed on a substrate is provided. The source and the drain respectively cover portions of the channel area. The reflective pixel electrode connects the drain and covers the bumps to form an uneven surface. The overcoat dielectric layer disposed on a transistor constituted by the gate, the gate dielectric layer, the patterned semiconductor layer, the source and the drain has a contact opening exposing a portion of the reflective pixel electrode. The transparent pixel electrode is electrically connected to the reflective pixel electrode through the contact opening.

Abstract translation: 一种像素结构，包括栅极，栅极电介质层，具有设置在栅极上方的沟道区域的图案化半导体层，具有设置在栅极上方的蚀刻停止层和多个凸起的图案化电介质层，具有 提供反射像素电极，源极和漏极，外涂层电介质层和顺序地设置在基板上的透明像素电极。 源极和漏极分别覆盖沟道区域的部分。 反射像素电极连接漏极并覆盖凸块以形成不平坦的表面。 设置在由栅极，栅极电介质层，图案化半导体层，源极和漏极构成的晶体管上的外涂层电介质层具有暴露反射像素电极的一部分的接触开口。 透明像素电极通过接触开口电连接到反射像素电极。

公开(公告)号：US20100144071A1

公开(公告)日：2010-06-10

申请号：US12704537

申请日：2010-02-12

Applicant: Hsiang-Lin Lin ,  Sung-Kao Liu

Inventor： Hsiang-Lin Lin ,  Sung-Kao Liu

IPC: H01L33/00

CPC classification number: G02F1/136227 ,  G02F1/136213 ,  G02F2001/13606 ,  G02F2001/136218

Abstract: A method of manufacturing a pixel structure is provided. A first patterned conductive layer including a gate and a data line is formed on a substrate. A gate insulating layer is formed to cover the first patterned conductive layer and a semiconductor channel layer is formed on the gate insulating layer above the gate. A second patterned conductive layer including a scan line, a common line, a source and a drain is formed on the gate insulating layer and the semiconductor channel layer. The scan line is connected to the gate and the common line is located above the data line. The source and drain are located on the semiconductor channel layer, and the source is connected to the data line. A passivation layer is formed on the substrate to cover the second patterned conductive layer. A pixel electrode connected to the drain is formed on the passivation layer.

Abstract translation: 提供了一种制造像素结构的方法。 在基板上形成包括栅极和数据线的第一图案化导电层。 形成栅极绝缘层以覆盖第一图案化导电层，并且在栅极上方的栅极绝缘层上形成半导体沟道层。 包括扫描线，公共线，源极和漏极的第二图案化导电层形成在栅极绝缘层和半导体沟道层上。 扫描线连接到栅极，公共线位于数据线上方。 源极和漏极位于半导体沟道层上，源极连接到数据线。 在衬底上形成钝化层以覆盖第二图案化导电层。 连接到漏极的像素电极形成在钝化层上。

公开(公告)号：US20100133542A1

公开(公告)日：2010-06-03

申请号：US12700678

申请日：2010-02-04

Applicant: Hsiang-Lin Lin ,  Sung-Kao Liu

Inventor： Hsiang-Lin Lin ,  Sung-Kao Liu

IPC: H01L33/00

CPC classification number: G02F1/136227 ,  G02F1/136213 ,  G02F2001/13606 ,  G02F2001/136218

Abstract: A method of manufacturing a pixel structure is provided. A first patterned conductive layer including a gate and a data line is formed on a substrate. A gate insulating layer is formed to cover the first patterned conductive layer and a semiconductor channel layer is formed on the gate insulating layer above the gate. A second patterned conductive layer including a scan line, a common line, a source and a drain is formed on the gate insulating layer and the semiconductor channel layer. The scan line is connected to the gate and the common line is located above the data line. The source and drain are located on the semiconductor channel layer, and the source is connected to the data line. A passivation layer is formed on the substrate to cover the second patterned conductive layer. A pixel electrode connected to the drain is formed on the passivation layer.