公开(公告)号：US11362968B2

公开(公告)日：2022-06-14

申请号：US15640258

申请日：2017-06-30

Applicant: Intel Corporation

Inventor： Ren Wang ,  Mia Primorac ,  Tsung-Yuan C. Tai ,  Saikrishna Edupuganti ,  John J. Browne

IPC: H04L12/861 ,  H04L49/90 ,  H04L47/36 ,  H04L49/9005

Abstract: Technologies for dynamically managing a batch size of packets include a network device. The network device is to receive, into a queue, packets from a remote node to be processed by the network device, determine a throughput provided by the network device while the packets are processed, determine whether the determined throughput satisfies a predefined condition, and adjust a batch size of packets in response to a determination that the determined throughput satisfies a predefined condition. The batch size is indicative of a threshold number of queued packets required to be present in the queue before the queued packets in the queue can be processed by the network device.

公开(公告)号：US11327735B2

公开(公告)日：2022-05-10

申请号：US16235598

申请日：2018-12-28

Applicant: Intel Corporation

Inventor： Ned M. Smith ,  Kshitij Arun Doshi ,  John J. Browne ,  Vincent J. Zimmer ,  Francesc Guim Bernat ,  Kapil Sood

IPC: G06F8/65 ,  G06F21/44 ,  G06F21/64 ,  H04L9/12 ,  H04L9/14 ,  H04L29/06 ,  H04L9/32 ,  H04L9/08

Abstract: Various systems and methods for enabling derivation and distribution of an attestation manifest for a software update image are described. In an example, these systems and methods include orchestration functions and communications, providing functionality and components for a software update process which also provides verification and attestation among multiple devices and operators.

公开(公告)号：US20220129031A1

公开(公告)日：2022-04-28

申请号：US17520296

申请日：2021-11-05

Applicant: Intel Corporation

Inventor： Vasudevan Srinivasan ,  Krishnakanth V. Sistla ,  Corey D. Gough ,  Ian M. Steiner ,  Nikhil Gupta ,  Vivek Garg ,  Ankush Varma ,  Sujal A. Vora ,  David P. Lerner ,  Joseph M. Sullivan ,  Nagasubramanian Gurumoorthy ,  William J. Bowhill ,  Venkatesh Ramamurthy ,  Chris MacNamara ,  John J. Browne ,  Ripan Das

IPC: G06F1/08 ,  G06F1/3203 ,  G06F9/30 ,  G06F9/455 ,  G06F1/324

Abstract: A processing device includes a plurality of processing cores, a control register, associated with a first processing core of the plurality of processing cores, to store a first base clock frequency value at which the first processing core is to run, and a power management circuit to receive a base clock frequency request comprising a second base clock frequency value, store the second base clock frequency value in the control register to cause the first processing core to run at the second base clock frequency value, and expose the second base clock frequency value on a hardware interface associated with the power management circuit.

公开(公告)号：US20210320881A1

公开(公告)日：2021-10-14

申请号：US17359303

申请日：2021-06-25

Applicant: Intel Corporation

Inventor： David Coyle ,  Brendan Ryan ,  John J. Browne ,  Jeffery G. Oliver ,  Pallavi Manaji Kadam ,  Sunku Ranganath

IPC: H04L12/863 ,  H04L12/861 ,  H04L12/851 ,  H04L12/825 ,  H04L12/927 ,  H04L12/911

Abstract: In one embodiment, a system comprising a network interface controller comprising circuitry to determine per-flow analytics information for a plurality of packet flows; and facilitate differential rate processing of a plurality of packet queues for the plurality of packet flows based on the per-flow analytics information.

公开(公告)号：US11050682B2

公开(公告)日：2021-06-29

申请号：US15719081

申请日：2017-09-28

Applicant: Intel Corporation

Inventor： Tomasz Kantecki ,  Niall Power ,  John J. Browne ,  Christopher MacNamara ,  Stephen Doyle

IPC: H04L12/861 ,  H04L12/883 ,  H04L12/801 ,  H04L12/935

Abstract: A network interface device, including: an ingress interface; a host platform interface to communicatively couple to a host platform; and a packet preprocessor including logic to: receive via the ingress interface a data sequence including a plurality of discrete data units; identify the data sequence as data for a parallel processing operation; reorder the discrete data units into a reordered data frame, the reordered data frame configured to order the discrete data units for consumption by the parallel operation; and send the reordered data to the host platform via the host platform interface.

公开(公告)号：US20210153019A1

公开(公告)日：2021-05-20

申请号：US17076452

申请日：2020-10-21

Applicant: Intel Corporation

Inventor： Alexander Bachmutsky ,  Dario Sabella ,  Francesc Guim Bernat ,  John J. Browne ,  Kapil Sood ,  Kshitij Arun Doshi ,  Mats Gustav Agerstam ,  Ned M. Smith ,  Rajesh Poornachandran ,  Tarun Viswanathan

IPC: H04W12/08 ,  H04W76/10 ,  H04W28/02 ,  G06F9/455 ,  H04W4/46 ,  H04L29/08 ,  H04W12/42 ,  H04W12/60 ,  H04W12/06

Abstract: A service coordinating entity device includes communications circuitry to communicate with a first access network, processing circuitry, and a memory device. The processing circuitry is to perform operations to, in response to a request for establishing a connection with a user equipment (UE) in a second access network, retrieve a first Trusted Level Agreement (TLA) including trust attributes associated with the first access network. One or more exchanges of the trust attributes of the first TLA and trust attributes of a second TLA associated with the second access network are performed using a computing service executing on the service coordinating entity. A common TLA with trust attributes associated with communications between the first and second access networks is generated based on the exchanges. Data traffic is routed from the first access network to the UE in the second access network based on the trust attributes of the common TLA.

公开(公告)号：US20210119878A1

公开(公告)日：2021-04-22

申请号：US17116858

申请日：2020-12-09

Applicant: Intel Corporation

Inventor： Ciara Loftus ,  John J. Browne ,  Timothy Verrall ,  Patrick G. Kutch ,  Chris M. Macnamara ,  Brendan Ryan ,  Dave Cremins ,  Andrey Chilikin

IPC: H04L12/24 ,  H04L12/26 ,  G06F9/455

Abstract: Telemetry information provided by a computing device includes switching key performance indicators (KPIs), platform KPIs, and topology information. The telemetry information is used to identify performance issues at the computing device, such as packets being dropped in a virtual switching stack or misconfiguration errors. A virtual switching monitor can identify which layers in the switching stack have errors and whether the errors occur along a transmit or receive path in the switching stack. A virtual switching controller can identify remedial actions that can be taken at the computing device to remedy a performance issue. A remedial action can be taken automatically, subject to user approval, or automatically after additional criteria are met.

公开(公告)号：US20210075732A1

公开(公告)日：2021-03-11

申请号：US16953210

申请日：2020-11-19

Applicant: Intel Corporation

Inventor： Jasvinder Singh ,  Thomas Long ,  Eoin Walsh ,  John J. Browne

IPC: H04L12/851 ,  H04L12/865 ,  H04L12/869 ,  H04L12/863 ,  H04L12/927

Abstract: In one embodiment, a system comprises an interface to receive a plurality of packets; and a plurality of processor units to execute a plurality of transmission sub-interfaces, each transmission sub-interface to perform hierarchical quality of service (HQoS) scheduling on a distinct subset of the plurality of packets, wherein each transmission sub-interface is to schedule its subset of the plurality of packets for transmission by a network interface controller by assigning the packets of the subset to a plurality of transmission queues that each correspond to a distinct traffic class.

公开(公告)号：US20190229897A1

公开(公告)日：2019-07-25

申请号：US16368982

申请日：2019-03-29

Applicant: Intel Corporation

Inventor： Timothy Verrall ,  Thomas Willhalm ,  Francesc Guim Bernat ,  Karthik Kumar ,  Ned M. Smith ,  Rajesh Poornachandran ,  Kapil Sood ,  Tarun Viswanathan ,  John J. Browne ,  Patrick Kutch

IPC: H04L9/08

Abstract: Technologies for accelerated key caching in an edge hierarchy include multiple edge appliance devices organized in tiers. An edge appliance device receives a request for a key, such as a private key. The edge appliance device determines whether the key is included in a local key cache and, if not, requests the key from an edge appliance device included in an inner tier of the edge hierarchy. The edge appliance device may request the key from an edge appliance device included in a peer tier of the edge hierarchy. The edge appliance device may activate per-tenant accelerated logic to identify one or more keys in the key cache for eviction. The edge appliance device may activate per-tenant accelerated logic to identify one or more keys for pre-fetching. Those functions of the edge appliance device may be performed by an accelerator such as an FPGA. Other embodiments are described and claimed.

公开(公告)号：US10341264B2

公开(公告)日：2019-07-02

申请号：US15199110

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： John J. Browne ,  Tomasz Kantecki ,  Chris MacNamara ,  Pierre Laurent ,  Sean Harte

IPC: H04L12/879 ,  H04L12/43 ,  H04L12/927 ,  H04L12/935 ,  H04L12/861

Abstract: Technologies for scalable packet reception and transmission include a network device. The network device is to establish a ring that is defined as a circular buffer and includes a plurality of slots to store entries representative of packets. The network device is also to generate and assign receive descriptors to the slots in the ring. Each receive descriptor includes a pointer to a corresponding memory buffer to store packet data. The network device is further to determine whether the NIC has received one or more packets and copy, with direct memory access (DMA) and in response to a determination that the NIC has received one or more packets, packet data of the received one or more packets from the NIC to the memory buffers associated with the receive descriptors assigned to the slots in the ring.