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    Multilane variable bias for an optical modulator
    92.
    发明授权
    Multilane variable bias for an optical modulator 有权
    用于光调制器的多硅可变偏置

    公开(公告)号：US09584884B1

    公开(公告)日：2017-02-28

    申请号：US14310962

    申请日：2014-06-20

    Applicant: INPHI CORPORATION

    Inventor： Radhakrishnan L. Nagarajan

    IPC: H04Q11/00

    CPC classification number: H04Q11/0005 ,  H04B10/40 ,  H04B10/5161 ,  H04B10/541 ,  H04Q11/0062 ,  H04Q2011/0016 ,  H04Q2011/0083 ,  H04Q2011/0096

    Abstract: In an example, the present invention includes an integrated system on chip device. The device has a variable bias block configured with the control block, the variable bias block being configured to selectively tune each of a plurality of laser devices provided on the silicon photonics device to adjust for at least a wavelength of operation, a fabrication tolerance, and an extinction ratio.

    Abstract translation: 在一个示例中，本发明包括集成片上系统设备。 所述器件具有由所述控制块配置的可变偏置块，所述可变偏置块被配置为选择性调谐设置在所述硅光子器件上的多个激光器件中的每一个，以调整至少波长的操作，制造公差和 消光比。

    Driver module for mach zehnder modulator
    93.
    发明授权
    Driver module for mach zehnder modulator 有权
    马赫祖德调制器的驱动模块

    公开(公告)号：US09553673B1

    公开(公告)日：2017-01-24

    申请号：US14798322

    申请日：2015-07-13

    Applicant: Inphi Corporation

    Inventor： Radhakrishnan L. Nagarajan ,  Todd Rope

    IPC: H04B10/00 ,  H04B10/524 ,  H03M1/68

    CPC classification number: H04B10/5161 ,  G02F1/0123 ,  G02F1/2255 ,  G02F1/2257 ,  G02F2001/212 ,  H03M1/682 ,  H04B10/524 ,  H04B10/541

    Abstract: A single chip dual-channel driver for two independent traveling wave modulators. The driver includes two differential pairs inputs per channel respectively configured to receive two digital differential pair signals. The driver further includes a two-bit DAC per channel coupled to the two differential pairs inputs to produce a single analog differential pair PAM signal at a differential pair output for driving a traveling wave modulator. Additionally, the driver includes a control block having internal voltage/current signal generators respective coupled to each input and the 2-bit DAC for providing a bias voltage, a tail current, a dither signal to assist modulation control per channel. Furthermore, the driver includes an internal I2C communication block coupled to a high-speed clock generator to generate control signals to the control block and coupled to host via an I2C digital communication interface.

    Abstract translation: 用于两个独立行波调制器的单芯片双通道驱动器。 驱动器包括每个通道的两个差分对输入，分别配置为接收两个数字差分对信号。 驱动器还包括耦合到两个差分对输入的每个通道的两位DAC，以在用于驱动行波调制器的差分对输出处产生单个模拟差分对PAM信号。 此外，驱动器包括具有各自耦合到每个输入的内部电压/电流信号发生器的控制块和用于提供偏置电压的2位DAC，尾部电流，抖动信号以辅助每个通道的调制控制。 此外，驱动器包括耦合到高速时钟发生器的内部I2C通信块，以产生到控制块的控制信号并通过I2C数字通信接口耦合到主机。

    Integrated control for silicon photonics
    94.
    发明授权
    Integrated control for silicon photonics 有权
    硅光子学的集成控制

    公开(公告)号：US09553672B1

    公开(公告)日：2017-01-24

    申请号：US15268239

    申请日：2016-09-16

    Applicant: INPHI CORPORATION

    Inventor： Radhakrishnan L. Nagarajan

    IPC: H04B10/04 ,  H04B10/40 ,  H04B10/556 ,  H04B10/54 ,  H03L7/08

    CPC classification number: H04B10/40 ,  H01S5/0261 ,  H01S5/0427 ,  H03L7/0807 ,  H03L2207/50 ,  H04B10/07955 ,  H04B10/541 ,  H04B10/5561 ,  H04B10/70 ,  H04B10/801 ,  H04J14/0221 ,  H04L49/109

    Abstract: In an example, the present invention includes an integrated system on chip device. The device is configured on a single silicon substrate member. The device has a data input/output interface provided on the substrate member. The device has an input/output block provided on the substrate member and coupled to the data input/output interface. The device has a signal processing block provided on the substrate member and coupled to the input/output block. The device has a driver module provided on the substrate member and coupled to the signal processing block. In an example, the device has a driver interface provided on the substrate member and coupled to the driver module and configured to be coupled to a silicon photonics device. The device also has an interface configured to communicate between the silicon photonics device and the control block.

    Abstract translation: 在一个示例中，本发明包括集成片上系统设备。 该器件配置在单个硅衬底构件上。 该设备具有设置在基板部件上的数据输入/输出接口。 该装置具有设置在基板部件上并与数据输入/输出接口耦合的输入/输出块。 该装置具有设置在基板构件上并耦合到输入/输出块的信号处理块。 该装置具有设置在基板部件上并与信号处理块相连的驱动器模块。 在一个示例中，该设备具有设置在该衬底构件上的驱动器接口并且耦合到该驱动器模块并被配置为耦合到硅光子器件。 该器件还具有被配置为在硅光子器件和控制块之间通信的接口。

    Configurable multi-rate format for communication system for silicon photonics
    95.
    发明授权
    Configurable multi-rate format for communication system for silicon photonics 有权
    硅光子通信系统的可配置多速率格式

    公开(公告)号：US09549232B1

    公开(公告)日：2017-01-17

    申请号：US14311033

    申请日：2014-06-20

    Applicant: INPHI CORPORATION

    Inventor： Radhakrishnan L. Nagarajan

    IPC: H04Q11/00

    CPC classification number: H04Q11/0005 ,  G02B6/122 ,  G02B2006/12097 ,  H04B10/5161 ,  H04B10/801 ,  H04J14/02 ,  H04Q11/0062 ,  H04Q2011/0016 ,  H04Q2011/0018 ,  H04Q2011/009 ,  H04Q2011/0096

    Abstract: In an example, the present invention includes an integrated system on chip device. The device has a data input/output interface provided on the substrate member and configured for a predefined data rate and protocol. In an example, the data input/output interface is configured for number of lanes numbered from four to one hundred and fifty. In an example, the SerDes block is configured to convert a first data stream of N into a second data stream of M such that each of the first data stream having a first predefined data rate at a first clock rate and each of the second data stream having a second predefined data rate at a second clock rate.

    Abstract translation: 在一个示例中，本发明包括集成片上系统设备。 设备具有设置在基板部件上的数据输入/输出接口，并且被配置为预定义的数据速率和协议。 在一个示例中，数据输入/输出接口被配置为编号从四到一百五十的通道数。 在一个示例中，SerDes块被配置为将N的第一数据流转换为M的第二数据流，使得第一数据流中的每一个具有第一时钟速率的第一预定数据速率和每个第二数据流 具有第二时钟速率的第二预定数据速率。

    Built-in self test for silicon photonics device
    98.
    发明授权
    Built-in self test for silicon photonics device 有权
    硅光子器件内置自检

    公开(公告)号：US09006740B1

    公开(公告)日：2015-04-14

    申请号：US14310374

    申请日：2014-06-20

    Applicant: Inphi Corporation

    Inventor： Radhakrishnan L. Nagarajan

    IPC: H04B10/07 ,  H04B10/073 ,  H04B10/80

    CPC classification number: H04B10/0731 ,  H04B10/40 ,  H04B10/502 ,  H04B10/503 ,  H04B10/803

    Abstract: In an example, the present invention includes an integrated system on chip device. The device has a self test block configured on the silicon photonics device and to be operable during a test operation, the self test block comprising a broad band source configured to emit electromagnetic radiation from 1200 nm to 1400 nm or 1500 to 1600 nm to a multiplexer device. In an example, a self test output is configured to a spectrum analyzer device external to the silicon photonics device.

    Abstract translation: 在一个示例中，本发明包括集成片上系统设备。 该装置具有在硅光子器件上配置的自测试块，并且在测试操作期间可操作，该自测试块包括被配置为向1200nm至1400nm或1500至1600nm的电磁辐射发射到多路复用器的宽带源 设备。 在一个示例中，自测试输出被配置到硅光子器件外部的频谱分析仪器。

    Method for co-packaging light engine chiplets on switch substrate
    99.
    发明授权
    Method for co-packaging light engine chiplets on switch substrate 有权

    公开(公告)号：US11165509B1

    公开(公告)日：2021-11-02

    申请号：US16894622

    申请日：2020-06-05

    Applicant: INPHI CORPORATION

    Inventor： Radhakrishnan L. Nagarajan ,  Liang Ding ,  Mark Patterson ,  Roberto Coccioli ,  Steve Aboagye

    IPC: H04B10/80 ,  H04B10/40 ,  H04J14/02 ,  H01L23/538 ,  H04B10/50

    Abstract: A method for co-packaging multiple light engines in a switch module is provided. The method includes providing a module substrate with a minimum lateral dimension no greater than 110 mm. The module substrate is configured with a first mounting site at a center region and a plurality of second mounting sites distributed densely along the peripheral sides. The method includes disposing a main die with a switch processor chip at the first mounting site. The switch processor chip is configured to operate with a digital-signal processing (DSP) interface for extra-short-reach data interconnect. The method further includes mounting a plurality of chiplet dies respectively into the plurality of second mounting sites. Each chiplet die is configured to be a packaged light engine with a minimum lateral dimension to allow a maximum number of chiplet dies with

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