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    Compact optical module integrated for communicating cryptocurrency transaction
    1.
    发明授权
    Compact optical module integrated for communicating cryptocurrency transaction 有权

    公开(公告)号：US10924269B1

    公开(公告)日：2021-02-16

    申请号：US16053715

    申请日：2018-08-02

    Applicant: INPHI CORPORATION

    Inventor： Liang Ding ,  Radhakrishnan L. Nagarajan ,  Roberto Coccioli

    IPC: H04L9/08 ,  H04B10/70 ,  H05K1/02 ,  G02B6/12 ,  G06Q20/06

    Abstract: A compact optical transceiver formed by hybrid multichip integration. The optical transceiver includes a Si-photonics chip attached on a PCB. Additionally, the optical transceiver includes a first TSV interposer and a second TSV interposer separately attached nearby the Si-photonics chip on the PCB. Furthermore, the optical transceiver includes a driver chip flip-bonded partially on the Si-photonics chip through a first sets of bumps and partially on the first TSV interposer through a second sets of bumps. Moreover, the optical transceiver includes a transimpedance amplifier module chip flip-bonded partially on the Si-photonics chip through a third sets of bumps and partially on the second TSV interposer through a fourth set of bumps.

    Vertical integration of hybrid waveguide with controlled interlayer thickness
    3.
    发明授权
    Vertical integration of hybrid waveguide with controlled interlayer thickness 有权

    公开(公告)号：US10107961B2

    公开(公告)日：2018-10-23

    申请号：US15855655

    申请日：2017-12-27

    Applicant: INPHI CORPORATION

    Inventor： Liang Ding ,  Radhakrishnan L. Nagarajan

    IPC: H01L21/76 ,  G02B6/132 ,  G02B6/125 ,  G02B6/136 ,  G02B6/122 ,  G02B6/12

    Abstract: An silicon photonics device of hybrid waveguides having a coupling interlayer with an accurately controlled thickness and a method of making the same. The device includes a first plurality of Si waveguides formed in a SOI substrate and a first layer of SiO2 overlying the first plurality of Si waveguides and a second plurality of Si3N4 waveguides formed on the first layer of SiO2. At least one Si3N4 waveguide is disposed partially overlapping with at least one of the first plurality Si waveguides in vertical direction separated by the first layer of SiO2 with a thickness controlled no greater than 90 nm. The device includes a second layer of SiO2 overlying the second plurality of Si3N4 waveguides. The method of accurately controlling the coupling interlayer SiO2 thickness includes a multilayer SiO2/Si3N4/SiO2 hard mask process for SiO2 etching and polishing as stopping and buffering layer as well as Si waveguide etching mask.

    Method for co-packaging light engine chiplets on switch substrate
    5.
    发明授权
    Method for co-packaging light engine chiplets on switch substrate 有权

    公开(公告)号：US11165509B1

    公开(公告)日：2021-11-02

    申请号：US16894622

    申请日：2020-06-05

    Applicant: INPHI CORPORATION

    Inventor： Radhakrishnan L. Nagarajan ,  Liang Ding ,  Mark Patterson ,  Roberto Coccioli ,  Steve Aboagye

    IPC: H04B10/80 ,  H04B10/40 ,  H04J14/02 ,  H01L23/538 ,  H04B10/50

    Abstract: A method for co-packaging multiple light engines in a switch module is provided. The method includes providing a module substrate with a minimum lateral dimension no greater than 110 mm. The module substrate is configured with a first mounting site at a center region and a plurality of second mounting sites distributed densely along the peripheral sides. The method includes disposing a main die with a switch processor chip at the first mounting site. The switch processor chip is configured to operate with a digital-signal processing (DSP) interface for extra-short-reach data interconnect. The method further includes mounting a plurality of chiplet dies respectively into the plurality of second mounting sites. Each chiplet die is configured to be a packaged light engine with a minimum lateral dimension to allow a maximum number of chiplet dies with

    Optical transceiver by FOWLP and DOP multichip integration
    6.
    发明授权
    Optical transceiver by FOWLP and DOP multichip integration 有权

    公开(公告)号：US10120150B2

    公开(公告)日：2018-11-06

    申请号：US15985584

    申请日：2018-05-21

    Applicant: INPHI CORPORATION

    Inventor： Liang Ding ,  Radhakrishnan L. Nagarajan ,  Roberto Coccioli

    IPC: G02B6/42 ,  G02B6/13 ,  G02B6/30 ,  H01L21/56 ,  H01L21/768 ,  H01L23/00 ,  H01L25/16 ,  G02B6/12

    Abstract: An optical transceiver by hybrid multichip integration. The optical transceiver includes a PCB with a plurality of prefabricated surface bonding sites. A first chip includes a FOWLP package of multiple electronics devices embedded in a dielectric molding layer overlying a dielectric redistribution layer is disposed on the PCB by respectively bonding a plurality of conductor balls between the dielectric redistribution layer and the plurality of prefabricated surface bonding sites while exposing soldering material filled in multiple through-mold vias (TMVs) in the dielectric molding layer. The optical transceiver further includes a second chip configured as a Sipho die comprising photonics devices embedded in a SOI wafer substantially free from any electronics device process. The second chip is stacked over the first chip with multiple conductor bumps being bonded respectively to the soldering material in the multiple TMVs.

    Vertical integration of hybrid waveguide with controlled interlayer thickness
    7.
    发明授权
    Vertical integration of hybrid waveguide with controlled interlayer thickness 有权

    公开(公告)号：US09671557B1

    公开(公告)日：2017-06-06

    申请号：US15061946

    申请日：2016-03-04

    Applicant: INPHI CORPORATION

    Inventor： Liang Ding ,  Radhakrishnan L. Nagarajan

    IPC: G02B6/12 ,  G02B6/122 ,  G02B6/132 ,  G02B6/136

    CPC classification number: G02B6/132 ,  G02B6/122 ,  G02B6/125 ,  G02B6/136 ,  G02B2006/12061

    Abstract: A silicon photonics device of hybrid waveguides having a coupling interlayer with an accurately controlled thickness and a method of making the same. The device includes a first plurality of Si waveguides formed in a SOI substrate and a first layer of SiO2 overlying the first plurality of Si waveguides and a second plurality of Si3N4 waveguides formed on the first layer of SiO2. At least one Si3N4 waveguide is disposed partially overlapping with at least one of the first plurality Si waveguides in vertical direction separated by the first layer of SiO2 with a thickness controlled no greater than 90 nm. The device includes a second layer of SiO2 overlying the second plurality of Si3N4 waveguides. The method of accurately controlling the coupling interlayer SiO2 thickness includes a multilayer SiO2/Si3N4/SiO2 hard mask process for SiO2 etching and polishing as stopping and buffering layer as well as Si waveguide etching mask.

    Light engine based on silicon photonics TSV interposer
    8.
    发明授权
    Light engine based on silicon photonics TSV interposer 有权

    公开(公告)号：US11367687B2

    公开(公告)日：2022-06-21

    申请号：US16738844

    申请日：2020-01-09

    Applicant: INPHI CORPORATION

    Inventor： Liang Ding ,  Radhakrishnan L. Nagarajan

    IPC: H01K3/10 ,  H01R43/00 ,  H01L23/34 ,  H01L23/48 ,  H01L21/00 ,  H01L23/538 ,  G02B6/42 ,  H01L25/16 ,  H01L23/00 ,  G02B6/12 ,  H01L21/768

    Abstract: A method for forming a silicon photonics interposer having through-silicon vias (TSVs). The method includes forming vias in a front side of a silicon substrate and defining primary structures for forming optical devices in the front side. Additionally, the method includes bonding a first handle wafer to the front side and thinning down the silicon substrate from the back side and forming bumps at the back side to couple with a conductive material in the vias. Furthermore, the method includes bonding a second handle wafer to the back side and debonding the first handle wafer from the front side to form secondary structures based on the primary structures. Moreover, the method includes forming pads at the front side to couple with the bumps at the back side before completing final structures based on the secondary structures and debonding the second handle wafer from the back side.

    Co-packaged light engine chiplets on switch substrate
    9.
    发明授权
    Co-packaged light engine chiplets on switch substrate 有权

    公开(公告)号：US11178473B1

    公开(公告)日：2021-11-16

    申请号：US16894611

    申请日：2020-06-05

    Applicant: INPHI CORPORATION

    Inventor： Radhakrishnan L. Nagarajan ,  Liang Ding ,  Mark Patterson ,  Roberto Coccioli ,  Steve Aboagye

    IPC: H04B10/00 ,  H04Q11/00 ,  G02B6/42

    Abstract: A co-packaged optical-electrical module includes a module substrate with a minimum lateral dimension no greater than 100 mm. The co-packaged optical-electrical module further includes a main die with a processor chip disposed at a central region of the module substrate, the processor chip being configured to operate with a digital-signal processing (DSP) interface for extra-short-reach data interconnect. Additionally, the co-packaged optical-electrical module includes a plurality of chiplet dies disposed densely along a peripheral region of the module substrate. Each chiplet die is configured to be self-packaged light engine on a sub-module substrate with a minimum lateral dimension to allow a maximum number of chiplet dies on the module substrate with a distance of any chiplet die from the main die smaller than 50 mm for extra-short-reach interconnect operation.

    Heatsink for co-packaged optical switch rack package
    10.
    发明授权
    Heatsink for co-packaged optical switch rack package 有权

    公开(公告)号：US11109515B1

    公开(公告)日：2021-08-31

    申请号：US16894639

    申请日：2020-06-05

    Applicant: INPHI CORPORATION

    Inventor： Radhakrishnan L. Nagarajan ,  Liang Ding ,  Mark Patterson ,  Roberto Coccioli ,  Steve Aboagye

    IPC: H05K7/20 ,  G02B6/42 ,  H01L23/427 ,  H01L25/16 ,  H04Q11/00 ,  G02B6/43

    Abstract: An integrated heatsink for a co-packaged optical-electrical module includes a base plate attached on top of a co-packaged optical-electrical module. The integrated heatsink further includes a plurality of fin structures extended upward from the base plate except a central cavity region with missing sections of fins, each fin extended along an axial direction from a front edge to a back edge of the base plate except some trenches shallow in depth across some fin structures and some other trenches deep in depth down to the base plate either along or across some fin structures. Additionally, the integrated heatsink includes multiple heat pipes including shaped portions embedded in the trenches in the plurality of fin structures. At least one bottom horizontal portion per heat pipe is brazed to the base plate in a corresponding region that is superimposed on hot spots of the co-packaged optical-electrical module under the base plate.

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