公开(公告)号：US6071782A

公开(公告)日：2000-06-06

申请号：US23383

申请日：1998-02-13

申请人： Jer-Shen Maa ,  Sheng Teng Hsu ,  Chien-Hsiung Peng

发明人： Jer-Shen Maa ,  Sheng Teng Hsu ,  Chien-Hsiung Peng

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/60 ,  H01L29/78 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L29/665 ,  H01L21/28052 ,  H01L29/6659

摘要： A process of forming silicide at uniform rates across the entire source/drain region is provided. A two-step annealing method permits the thickness of the silicide formed on the edge of a silicon electrode to be substantially the same as it is in the center of the electrode. A first, low temperature anneal begins the salicidation process across the source/drain electrode surface. The time and temperature are controlled so that the metal is only partially consumed. The annealing is interrupted to remove excess silicidation metal, especially the unreacted metal overlying oxide areas neighboring the silicon electrode. Then, the silicidation is completed at a higher temperature anneal. Because the excess metal has been removed, the resulting silicide layer is uniformly flat, permitting the transistor to be fabricated with shallow junction areas and low leakage currents. In one embodiment of the invention, the crystalline structure of source and drain surfaces is annihilated before the deposition of metal, to lower annealing temperatures and add precise control to the silicidation process. A transistor having a uniformly thick silicide layer, fabricated in accordance with the above-mentioned method, is also provided.

摘要翻译： 提供了在整个源极/漏极区域以均匀的速率形成硅化物的工艺。 两步退火方法允许形成在硅电极边缘上的硅化物的厚度与电极中心基本相同。 首先，低温退火开始跨越源/漏电极表面的盐析过程。 控制时间和温度，使得金属仅被部分消耗。 中断退火以去除过量的硅化金属，特别是覆盖与硅电极相邻的氧化物区域的未反应的金属。 然后，在较高温度的退火下完成硅化。 由于去除了多余的金属，所得到的硅化物层是均匀平坦的，从而允许晶体管被制造成具有浅结的区域和低的漏电流。 在本发明的一个实施例中，源极和漏极表面的晶体结构在金属沉积之前被消除，以降低退火温度并且增加对硅化工艺的精确控制。 还提供了具有根据上述方法制造的均匀厚的硅化物层的晶体管。

公开(公告)号：US6048740A

公开(公告)日：2000-04-11

申请号：US187238

申请日：1998-11-05

申请人： Sheng Teng Hsu ,  Jer-shen Maa ,  Fengyang Zhang ,  Tingkai Li

发明人： Sheng Teng Hsu ,  Jer-shen Maa ,  Fengyang Zhang ,  Tingkai Li

IPC分类号： H01L21/8247 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792 ,  H01L29/76

CPC分类号： H01L29/6684 ,  H01L29/78391

摘要： A method of fabricating a ferroelectric memory transistor using a lithographic process having an alignment tolerance of .delta., includes preparing a silicon substrate for construction of a ferroelectric gate unit; implanting boron ions to form a p- well in the substrate; isolating plural device areas on the substrate; forming a FE gate stack surround structure; etching the FE gate stack surround structure to form an opening having a width of L1 to expose the substrate in a gate region; depositing oxide to a thickness of between about 10 nm to 40 nm over the exposed substrate; forming a FE gate stack over the gate region, wherein the FE gate stack has a width of L2, wherein L2.gtoreq.L1+2.delta.; depositing a first insulating layer over the structure; implanting arsenic or phosphorous ions to form a source region and a drain region; annealing the structure; depositing a second insulating layer; and metallizing the structure. A ferroelectric memory transistor includes a silicon substrate having a p- well formed therein; a gate region, a source region and a drain region disposed along the upper surface of said substrate; a FE gate stack surround structure having an opening having a width of L1 located about said gate region; a FE gate stack formed in said FE gate stack surround structure, wherein said FE gate stack has a width of L2, wherein L2.gtoreq.L1+2.delta., wherein .delta. is the alignment tolerance of the lithographic process.

摘要翻译： 使用具有三角形对准公差的光刻工艺制造铁电存储晶体管的方法包括制备用于构造铁电栅极单元的硅衬底; 注入硼离子以在衬底中形成p-阱; 隔离基板上的多个器件区域; 形成一个FE门堆栈环绕结构; 蚀刻FE栅堆叠环绕结构以形成宽度为L1的开口，以在栅极区域中露出基板; 在暴露的衬底上沉积氧化物至约10nm至40nm的厚度; 在所述栅极区域上形成FE栅极堆叠，其中所述FE栅极堆叠具有L2的宽度，其中L2> / = L1 +2δ; 在所述结构上沉积第一绝缘层; 注入砷或磷离子以形成源区和漏区; 退火结构; 沉积第二绝缘层; 并且对结构进行金属化。 铁电存储晶体管包括其中形成有p-阱的硅衬底; 栅极区域，源极区域和漏极区域，沿着所述衬底的上表面设置; 具有开口的FE栅叠层环绕结构，所述开口具有围绕所述栅区的L1的宽度; 形成在所述FE栅极堆叠环绕结构中的FE栅极堆叠，其中所述FE栅极堆叠具有L2的宽度，其中L2> / = L1 +2δ，其中Δ是光刻工艺的对准公差。

公开(公告)号：US5989965A

公开(公告)日：1999-11-23

申请号：US23032

申请日：1998-02-13

申请人： Jer-Shen Maa ,  Sheng Teng Hsu ,  Chien-Hsiung Peng

发明人： Jer-Shen Maa ,  Sheng Teng Hsu ,  Chien-Hsiung Peng

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

CPC分类号： H01L29/6659 ,  H01L21/28052 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6656

摘要： A method of forming a temporary overhang structure to shield the source/drain edges near the gate electrode from the deposition of silicidation metal is provided. The growth of silicide on the source/drain regions remains controlled, without the presence of silicidation metal on the gate electrode sidewalls near the source/drain edges. The resulting silicide layer does not have edge growths interfering with the source/drain junction areas. The overhang structure is formed by covering the gate electrode with two insulators having differing etch selectivities. The top insulator is anisotropically etched so that only the top insulator covering the gate electrode vertical sidewalls remains. The exposed bottom insulator is isotropically etched to form a gap between the top insulator and the source/drain region surfaces. When silicidation metal is deposited, the gap prevents the deposition of metal between the gate electrode and the source/drain region surfaces. A transistor, with an overhang structure, fabricated by the above-mentioned procedure is also provided.

摘要翻译： 提供了形成临时突出结构以屏蔽栅电极附近的源/漏边缘与沉积硅化金属的方法。 源极/漏极区域上的硅化物的生长保持受控，而在源极/漏极边缘附近的栅电极侧壁上不存在硅化金属。 所得到的硅化物层不具有干扰源极/漏极结区域的边缘增长。 通过用具有不同蚀刻选择性的两个绝缘体覆盖栅电极来形成突出结构。 顶绝缘体被各向异性地蚀刻，使得仅覆盖覆盖栅电极垂直侧壁的顶绝缘体保留。 暴露的底部绝缘体被各向同性地蚀刻以在顶部绝缘体和源极/漏极区域表面之间形成间隙。 当沉积硅化金属时，间隙防止金属沉积在栅电极和源/漏区表面之间。 还提供了通过上述方法制造的具有突出结构的晶体管。

公开(公告)号：US5814537A

公开(公告)日：1998-09-29

申请号：US768647

申请日：1996-12-18

申请人： Jer-shen Maa ,  Sheng Teng Hsu

发明人： Jer-shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78 ,  H01L29/786 ,  H01L21/285

CPC分类号： H01L29/66772 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/665 ,  H01L2924/0002 ,  Y10S148/147

摘要： A method is provided for forming silicide surfaces on source, drain, and gate electrodes in active devices to decrease the resistance of the electrode surfaces, without consuming the silicon of the electrodes in the process. Silicide is directionally deposited on the electrodes so that a greater thickness accumulates on electrode surfaces, and a lesser thickness accumulates on the gate sidewall surfaces isolating the gate from the source/drain electrodes. Then, the electrodes are isotropically etched so that the lesser thickness on the sidewalls is removed, leaving at least some thickness of silicide covering the electrodes. In further steps, the electrodes are masked with photoresist, and any silicide deposited in the region of field oxide around the electrodes is removed. Conductive lines, connecting to the electrodes across the field oxide, are fabricated from polycide, which includes a level of polysilicon covered with silicide, when the lower resistance surface of a metal-disilicide overlying the conductive line is required. The method of the present invention is applicable to bulk silicon, as well as SIMOX, transistor fabrication processes. An IC structure having different thicknesses of directionally deposited silicide, and a completed MOS transistor having interim thicknesses of directionally deposited silicide, are also provided.

摘要翻译： 提供了一种用于在有源器件中的源极，漏极和栅电极上形成硅化物表面以降低电极表面的电阻而不消耗该工艺中的电极的硅的方法。 硅化物被定向沉积在电极上，使得更大的厚度积聚在电极表面上，并且较小的厚度积聚在栅极侧壁表面上，隔离栅极与源极/漏极电极。 然后，电极被各向同性地蚀刻，以便去除侧壁上较小的厚度，留下覆盖电极的至少一些厚度的硅化物。 在其他步骤中，电极被光致抗蚀剂掩蔽，并且去除沉积在电极周围的场氧化物区域中的任何硅化物。 当需要覆盖在导电线上的金属二硅化物的较低电阻表面时，由多晶硅半导体制造连接到场氧化物上的电极的导电线，其包括覆盖有硅化物的多晶硅层。 本发明的方法可应用于体硅，以及SIMOX晶体管制造工艺。 还提供了具有不同厚度的定向沉积的硅化物的IC结构和具有定向沉积的硅化物的中间厚度的完整的MOS晶体管。

公开(公告)号：US06998661B2

公开(公告)日：2006-02-14

申请号：US10385009

申请日：2003-03-10

申请人： Fengyan Zhang ,  Jer-Shen Maa ,  Wei-Wei Zhuang ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Jer-Shen Maa ,  Wei-Wei Zhuang ,  Sheng Teng Hsu

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/1136 ,  H01L31/119

CPC分类号： H01L28/65 ,  C23C16/40 ,  H01L21/31691 ,  H01L28/55 ,  H01L28/56 ,  H01L28/60 ,  H01L28/75 ,  Y10T428/24917 ,  Y10T428/2495

摘要： A method of forming an electrode and a ferroelectric thin film thereon, includes preparing a substrate; depositing an electrode on the substrate, wherein the electrode is formed of a material taken from the group of materials consisting of iridium and iridium composites; and forming a single-phase, c-axis PGO ferroelectric thin film thereon, wherein the ferroelectric thin film exhibits surface smoothness and uniform thickness. An integrated circuit includes a substrate; an electrode deposited on the substrate, wherein the electrode is formed of a material taken from the group of materials consisting of iridium and iridium composites, wherein the iridium composites are taken from the group of composites consisting of IrO2, Ir—Ta—O, Ir—Ti—O, Ir—Nb—O, Ir—Al—O, Ir—Hf—O, Ir—V—O, Ir—Zr—O and Ir—O; and a single-phase, c-axis PGO ferroelectric thin film formed on the electrode, wherein the ferroelectric thin film exhibits surface smoothness and uniform thickness.

摘要翻译： 一种在其上形成电极和铁电薄膜的方法，包括制备基板; 在所述基板上沉积电极，其中所述电极由从由铱和铱复合材料组成的材料组取得的材料形成; 并在其上形成单相c轴PGO铁电薄膜，其中铁电薄膜表现出平滑度和均匀的厚度。 集成电路包括基板; 沉积在所述基底上的电极，其中所述电极由从由铱和铱复合物组成的材料组中取得的材料形成，其中所述铱复合材料取自由IrO 2 ，Ir-Ta-O，Ir-Ti-O，Ir-Nb-O，Ir-Al-O，Ir-Hf-O，Ir-VO，Ir-Zr-O和Ir-O; 以及形成在电极上的单相c轴PGO铁电薄膜，其中铁电薄膜表现出平滑度和均匀的厚度。

公开(公告)号：US06627919B2

公开(公告)日：2003-09-30

申请号：US10319312

申请日：2002-12-12

申请人： Jer-shen Maa ,  Douglas James Tweet ,  Sheng Teng Hsu

发明人： Jer-shen Maa ,  Douglas James Tweet ,  Sheng Teng Hsu

IPC分类号： H01L2976

CPC分类号： H01L21/28525 ,  H01L21/28518 ,  H01L29/45

摘要： A thermally stable nickel germanosilicide on SiGe integrated circuit device, and a method of making the same, is disclosed. During fabrication of the device iridium or cobalt is added at the Ni/SiGe interface to decrease the sheet resistance of the device. The device comprising nickel silicide with iridium on SiGe shows thermal stability at temperatures up to 800° C. The device comprising nickel silicide with cobalt on SiGe shows a decrease in the sheet resistance with temperature, i.e., the resistance remains low when annealing temperatures extend up to and beyond 800° C.

公开(公告)号：US06586260B2

公开(公告)日：2003-07-01

申请号：US09820078

申请日：2001-03-28

申请人： Fengyan Zhang ,  Jer-Shen Maa ,  Wei-Wei Zhuang ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Jer-Shen Maa ,  Wei-Wei Zhuang ,  Sheng Teng Hsu

IPC分类号： H01L2100

CPC分类号： H01L28/65 ,  C23C16/40 ,  H01L21/31691 ,  H01L28/55 ,  H01L28/56 ,  H01L28/60 ,  H01L28/75 ,  Y10T428/24917 ,  Y10T428/2495

摘要： A method of forming an electrode and a ferroelectric thin film thereon, includes preparing a substrate; depositing an electrode on the substrate, wherein the electrode is formed of a material taken from the group of materials consisting of iridium and iridium composites; and forming a single-phase, c-axis PGO ferroelectric thin film thereon, wherein the ferroelectric thin film exhibits surface smoothness and uniform thickness. An integrated circuit includes a substrate; an electrode deposited on the substrate, wherein the electrode is formed of a material taken from the group of materials consisting of iridium and iridium composites, wherein the iridium composites are taken from the group of composites consisting of IrO2, Ir—Ta—O, Ir—Ti—O, Ir—Nb—O, Ir—Al—O, Ir—Hf—O, Ir—V—O, Ir—Zr—O and Ir—O; and a single-phase, c-axis PGO ferroelectric thin film formed on the electrode, wherein the ferroelectric thin film exhibits surface smoothness and uniform thickness.

公开(公告)号：US06462366B1

公开(公告)日：2002-10-08

申请号：US09481674

申请日：2000-01-12

申请人： Sheng Teng Hsu ,  Jer-shen Maa ,  Fengyan Zhang ,  Tingkai Li

发明人： Sheng Teng Hsu ,  Jer-shen Maa ,  Fengyan Zhang ,  Tingkai Li

IPC分类号： H01L2976

CPC分类号： H01L29/6684 ,  H01L29/78391

摘要： A method of fabricating a ferroelectric memory transistor using a lithographic process having an alignment tolerance of &dgr;, includes preparing a silicon substrate for construction of a ferroelectric gate unit; implanting boron ions to form a p-well in the substrate; isolating plural device areas on the substrate; forming a FE gate stack surround structure; etching the FE gate stack surround structure to form an opening having a width of L1 to expose the substrate in a gate region; depositing oxide to a thickness of between about 10 nm to 40 nm over the exposed substrate; forming a FE gate stack over the gate region, wherein the FE gate stack has a width of L2, wherein L2≧L1+2&dgr;; depositing a first insulating layer over the structure; implanting arsenic or phosphorous ions to form a source region and a drain region; annealing the structure; depositing a second insulating layer; and metallizing the structure. A ferroelectric memory transistor includes a silicon substrate having a p-well formed therein; a gate region, a source region and a drain region disposed along the upper surface of said substrate; a FE gate stack surround structure having an opening having a width of L1 located about said gate region; a FE gate stack formed in said FE gate stack surround structure, wherein said FE gate stack has a width of L2, wherein L2≧L1+2&dgr;, wherein &dgr; is the alignment tolerance of the lithographic process.

摘要翻译： 使用具有三角形对准公差的光刻工艺制造铁电存储晶体管的方法包括制备用于构造铁电栅极单元的硅衬底; 注入硼离子以在衬底中形成p阱; 隔离基板上的多个器件区域; 形成一个FE门堆栈环绕结构; 蚀刻FE栅堆叠环绕结构以形成宽度为L1的开口，以在栅极区域中露出基板; 在暴露的衬底上沉积氧化物至约10nm至40nm的厚度; 在所述栅极区域上形成FE栅极堆叠，其中所述FE栅极堆叠具有L2的宽度，其中L2> = L1 + 2delta; 在所述结构上沉积第一绝缘层; 注入砷或磷离子以形成源区和漏区; 退火结构; 沉积第二绝缘层; 并且对所述结构进行金属化。铁电存储晶体管包括其中形成有p阱的硅衬底; 栅极区域，源极区域和漏极区域，沿着所述衬底的上表面设置; 具有开口的FE栅叠层环绕结构，所述开口具有围绕所述栅区的L1的宽度; 形成在所述FE栅极堆叠环绕结构中的FE栅极堆叠，其中所述FE栅极堆叠具有L2的宽度，其中L2> = L1 + 2delta，其中Δ是光刻工艺的对准公差。

公开(公告)号：US06372034B1

公开(公告)日：2002-04-16

申请号：US09687827

申请日：2000-10-12

申请人： Wei-Wei Zhuang ,  Jer-shen Maa ,  Fengyan Zhang ,  Sheng Teng Hsu

发明人： Wei-Wei Zhuang ,  Jer-shen Maa ,  Fengyan Zhang ,  Sheng Teng Hsu

IPC分类号： H01L2122

CPC分类号： H01L21/31691

摘要： A method of preparing a PGO solution for spin coating includes preparing a 2-methoxyethanol organic solvent; adding Pb(OCH3CO)2.3H2O to the organic solvent at ambient temperature and pressure in a nitrogen-filled glaved box to form Pb in methoxyethanol; refluxing the solution in a nitrogen atmosphere at 150° C. for at least two hours; fractionally distilling the refluxed solution at approximately 150° C. to remove all of the water from the solution; cooling the solution to room temperature; determining the Pb concentration of the solution; adding the 2-methoxyethanol solution to the Pb 2-methoxyethanol until a desired Pb concentration is achieved; combining Ge(OR)4, where R is taken the group of Rs consisting of CH2CH3 and CH(CH3)2, and 2-methoxyethanol; and adding Ge(OR)4 2-methoxyethanol to PbO 2-methoxyethanol to form the PGO solution having a predetermined metal ion concentration and a predetermined Pb:Ge molar ration.

摘要翻译： 制备用于旋涂的PGO溶液的方法包括制备2-甲氧基乙醇有机溶剂; 在环境温度和压力下，在氮气充填的玻璃箱中加入Pb（OCH 3 CO）2.3H 2 O至有机溶剂中以在甲氧基乙醇中形成Pb; 将溶液在氮气气氛中在150℃下回流至少2小时; 在大约150℃下将回流的溶液分馏，以从溶液中除去所有的水; 将溶液冷却至室温; 测定溶液的Pb浓度; 将2-甲氧基乙醇溶液加入到Pb 2-甲氧基乙醇中直到达到所需的Pb浓度; 组合Ge（OR）4，其中R是由CH 2 CH 3和CH（CH 3）2组成的基团和2-甲氧基乙醇; 并向PbO 2 - 甲氧基乙醇中加入Ge（OR）4 2-甲氧基乙醇以形成具有预定的金属离子浓度和预定的Pb:Ge摩尔比的PGO溶液。

公开(公告)号：US06368960B1

公开(公告)日：2002-04-09

申请号：US09113667

申请日：1998-07-10

申请人： Sheng Teng Hsu ,  Jer-Shen Maa

发明人： Sheng Teng Hsu ,  Jer-Shen Maa

IPC分类号： H01L21336

CPC分类号： H01L29/66757 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/665

摘要： A method of forming a silicided device includes preparing a substrate by forming device areas thereon; providing structures that are located between the substrate and any silicide layers; forming a first layer of a first reactive material over the formed structures; providing insulating regions in selected portions of the structure; forming a second layer of a second reactive material over the insulating regions and the first layer of first reactive material; reacting the first and second reactive materials to form silicide layers; removing any un-reacted reactive material; forming structures that are located on the silicide layers; and metallizing the device.

摘要翻译： 一种形成硅化器件的方法包括通过在其上形成器件区域来制备衬底; 提供位于衬底和任何硅化物层之间的结构; 在所形成的结构上形成第一反应性材料的第一层; 在结构的选定部分提供绝缘区域; 在所述绝缘区域和所述第一反应性材料层上形成第二反应性材料层; 使第一和第二反应性材料反应形成硅化物层; 去除任何未反应的反应性材料; 形成位于硅化物层上的结构; 并对该装置进行金属化。