公开(公告)号：US09371226B2

公开(公告)日：2016-06-21

申请号：US13019879

申请日：2011-02-02

Applicant: Robert V. Fox ,  Fengyan Zhang ,  Rene G. Rodriguez ,  Joshua J. Pak ,  Chivin Sun

Inventor： Robert V. Fox ,  Fengyan Zhang ,  Rene G. Rodriguez ,  Joshua J. Pak ,  Chivin Sun

IPC: H01L31/02 ,  H01L31/18 ,  C01B17/00 ,  B82Y30/00 ,  C01G15/00 ,  H01L31/032 ,  H01L31/0392 ,  H01L31/0749

CPC classification number: B82Y30/00 ,  C01G15/006 ,  C01P2002/72 ,  C01P2002/84 ,  C01P2004/62 ,  C01P2004/64 ,  C01P2006/40 ,  H01L31/0322 ,  H01L31/03923 ,  H01L31/0749 ,  Y02E10/541

Abstract: Single source precursors or pre-copolymers of single source precursors are subjected to microwave radiation to form particles of a I-III-VI2 material. Such particles may be formed in a wurtzite phase and may be converted to a chalcopyrite phase by, for example, exposure to heat. The particles in the wurtzite phase may have a substantially hexagonal shape that enables stacking into ordered layers. The particles in the wurtzite phase may be mixed with particles in the chalcopyrite phase (i.e., chalcopyrite nanoparticles) that may fill voids within the ordered layers of the particles in the wurtzite phase thus produce films with good coverage. In some embodiments, the methods are used to form layers of semiconductor materials comprising a I-III-VI2 material. Devices such as, for example, thin-film solar cells may be fabricated using such methods.

Abstract translation: 将单源前体或单源前体的预共聚物进行微波辐射以形成I-III-VI2材料的颗粒。 这样的颗粒可以以纤锌矿相形成，并且可以通过例如暴露于热而转变成黄铜矿相。 纤锌矿相中的颗粒可以具有基本上六边形的形状，其能够堆叠成有序层。 纤锌矿相中的颗粒可以与黄铜矿相中的颗粒（即，黄铜矿纳米颗粒）混合，其可以填充纤锌矿相中颗粒的有序层内的空隙，从而产生具有良好覆盖率的膜。 在一些实施例中，所述方法用于形成包含I-III-VI2材料的半导体材料层。 可以使用这样的方法来制造诸如薄膜太阳能电池的装置。

公开(公告)号：US07905013B2

公开(公告)日：2011-03-15

申请号：US11809959

申请日：2007-06-04

Applicant: Fengyan Zhang ,  Bruce D. Ulrich ,  Wei Gao ,  Sheng Teng Hsu

Inventor： Fengyan Zhang ,  Bruce D. Ulrich ,  Wei Gao ,  Sheng Teng Hsu

IPC: H01K3/10

CPC classification number: A61N1/0543 ,  B82Y15/00 ,  B82Y30/00 ,  Y10T29/49128 ,  Y10T29/4913 ,  Y10T29/49165 ,  Y10T29/49167 ,  Y10T29/49169 ,  Y10T428/24998

Abstract: An iridium oxide (IrOx) nanowire neural sensor array and associated fabrication method are provided. The method provides a substrate with a conductive layer overlying the substrate, and a dielectric layer overlying the conductive layer. The substrate can be a material such as Si, SiO2, quartz, glass, or polyimide, and the conductive layer is a material such as ITO, SnO2, ZnO, TiO2, doped ITO, doped SnO2, doped ZnO, doped TiO2, TiN, TaN, Au, Pt, or Ir. The dielectric layer is selectively wet etched, forming contact holes with sloped walls in the dielectric layer and exposing regions of the conductive layer. IrOx nanowire neural interfaces are grown from the exposed regions of the conductive layer. The IrOx nanowire neural interfaces each have a cross-section in a range of 0.5 to 10 micrometers, and may be shaped as a circle, rectangle, or oval.

Abstract translation: 提供氧化铱（IrOx）纳米线神经传感器阵列及相关制造方法。 该方法提供了具有覆盖在衬底上的导电层的衬底和覆盖导电层的电介质层。 基板可以是诸如Si，SiO 2，石英，玻璃或聚酰亚胺的材料，并且导电层是诸如ITO，SnO 2，ZnO，TiO 2，掺杂的ITO，掺杂的SnO 2，掺杂的ZnO，掺杂的TiO 2，TiN， TaN，Au，Pt或Ir。 电介质层被选择性地湿蚀刻，与电介质层中的倾斜壁形成接触孔并且暴露导电层的区域。 IrOx纳米线神经接口从导电层的暴露区域生长。 IrOx纳米线神经接口各自具有在0.5至10微米的范围内的横截面，并且可以被成形为圆形，矩形或椭圆形。

公开(公告)号：US20090024182A1

公开(公告)日：2009-01-22

申请号：US12240501

申请日：2008-09-29

Applicant: Fengyan Zhang ,  Sheng Teng Hsu

Inventor： Fengyan Zhang ,  Sheng Teng Hsu

IPC: A61N1/36

CPC classification number: C30B25/00 ,  A61N1/0543 ,  B82Y5/00 ,  B82Y10/00 ,  B82Y30/00 ,  C30B29/16 ,  C30B29/605 ,  Y10S977/811 ,  Y10S977/904 ,  Y10S977/932

Abstract: An optical device with an iridium oxide (IrOx) electrode neural interface, and a corresponding fabrication method are provided. The method provides a substrate and forms a first conductive electrode overlying the substrate. A photovoltaic device having a first electrical interface is connected to the first electrode. A second electrical interface of the photovoltaic device is connected to a second conductive electrode formed overlying the photovoltaic device. An array of neural interface single-crystal IrOx nanostructures are formed overlying the second electrode, where x≦4. The IrOx nanostructures can be partially coated with an electrical insulator, such as SiO2, SiN, TiO2, or spin on glass (SOG), leaving the IrOx distal ends exposed. In one aspect, a buffer layer is formed overlying the second electrode surface, made from a material such as LiNbO3, LiTaO3, or SA, for the purpose of orienting the growth direction of the IrOx nanostructures.

Abstract translation: 提供了具有氧化铱（IrOx）电极神经接口的光学器件及相应的制造方法。 该方法提供了一个衬底并且形成了覆盖衬底的第一导电电极。 具有第一电接口的光电器件连接到第一电极。 光电器件的第二电接口连接到形成在光伏器件上的第二导电电极。 形成了覆盖第二电极的神经界面单晶IrOx纳米结构阵列，其中x <= 4。 IrOx纳米结构可以部分地涂覆有电绝缘体，例如SiO 2，SiN，TiO 2或旋转玻璃（SOG），留下IrOx远端暴露。 在一个方面，为了定向IrOx纳米结构的生长方向，形成了由诸如LiNbO 3，LiTaO 3或SA的材料制成的第二电极表面上的缓冲层。

公开(公告)号：US07446014B2

公开(公告)日：2008-11-04

申请号：US11580623

申请日：2006-10-12

Applicant: Fengyan Zhang ,  David R. Evans ,  Sheng Teng Hsu

Inventor： Fengyan Zhang ,  David R. Evans ,  Sheng Teng Hsu

IPC: H01L21/20

CPC classification number: H01G9/07 ,  Y10S977/762 ,  Y10T29/417

Abstract: A method is provided for forming a NanoElectroChemical (NEC) cell. The method provides a bottom electrode with a top surface. Nanowire shells are formed. Each nanowire shell has a nanowire and a sleeve, with the nanowire connected to the bottom electrode top surface. A top electrode is formed overlying the nanowire shells. A main cavity is formed between the top electrode and bottom electrodes, partially displaced by a first plurality of nanowire shells. Electrolyte cavities are formed between the sleeves and nanowires by etching the first sacrificial layer. In one aspect, electrolyte cavities are formed between the bottom electrode top surface and a shell coating layer joining the sleeve bottom openings. Then, the main and electrolyte cavities are filled with either a liquid or gas phase electrolyte. In a different aspect, the first sacrificial layer is a solid phase electrolyte that is not etched away.

公开(公告)号：US07256429B2

公开(公告)日：2007-08-14

申请号：US11314222

申请日：2005-12-21

Applicant: Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei Pan ,  Wei-Wei Zhuang ,  David R. Evans ,  Masayuki Tajiri

Inventor： Sheng Teng Hsu ,  Tingkai Li ,  Fengyan Zhang ,  Wei Pan ,  Wei-Wei Zhuang ,  David R. Evans ,  Masayuki Tajiri

IPC: H01L21/00

CPC classification number: H01L27/101 ,  G11C13/0007 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2213/31 ,  G11C2213/51 ,  G11C2213/56 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/147

Abstract: A method is provided for forming a buffered-layer memory cell. The method comprises: forming a bottom electrode; forming a colossal magnetoresistance (CMR) memory film overlying the bottom electrode; forming a memory-stable semiconductor buffer layer, typically a metal oxide, overlying the memory film; and, forming a top electrode overlying the semiconductor buffer layer. In some aspects of the method the semiconductor buffer layer is formed from YBa2Cu3O7−X (YBCO), indium oxide (In2O3), or ruthenium oxide (RuO2), having a thickness in the range of 10 to 200 nanometers (nm). The top and bottom electrodes may be TiN/Ti, Pt/TiN/Ti, In/TiN/Ti, PtRhOx compounds, or PtIrOx compounds. The CMR memory film may be a Pr1−XCaXMnO3 (PCMO) memory film, where x is in the region between 0.1 and 0.6, with a thickness in the range of 10 to 200 nm.

Abstract translation: 提供了一种用于形成缓冲层存储单元的方法。 该方法包括：形成底部电极; 形成覆盖底部电极的巨大磁阻（CMR）记忆膜; 形成存储器稳定的半导体缓冲层，通常为覆盖存储膜的金属氧化物; 并且形成覆盖半导体缓冲层的顶部电极。 在该方法的一些方面，半导体缓冲层由YBa 2 N 3 O 7-X（YBCO），氧化铟（In 2或2 O 3）或氧化钌（RuO 2 N 2），其厚度在10-200纳米（nm）的范围内。 顶部和底部电极可以是TiN / Ti，Pt / TiN / Ti，In / TiN / Ti，PtRhOx化合物或PtIrOx化合物。 CMR存储器膜可以是Pr 1-X C x MnO 3（PCMO）存储膜，其中x在0.1之间的区域 和0.6，厚度在10至200nm的范围内。

公开(公告)号：US07255745B2

公开(公告)日：2007-08-14

申请号：US10971330

申请日：2004-10-21

Applicant: Fengyan Zhang ,  Robert A. Barrowcliff ,  Sheng Teng Hsu

Inventor： Fengyan Zhang ,  Robert A. Barrowcliff ,  Sheng Teng Hsu

IPC: C30B29/62

CPC classification number: H01L24/48 ,  C30B25/005 ,  C30B29/16 ,  C30B29/62 ,  H01L24/45 ,  H01L24/49 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/05669 ,  H01L2224/43827 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/45155 ,  H01L2224/45157 ,  H01L2224/45166 ,  H01L2224/45169 ,  H01L2224/45178 ,  H01L2224/45181 ,  H01L2224/45565 ,  H01L2224/45599 ,  H01L2224/45688 ,  H01L2224/48011 ,  H01L2224/48091 ,  H01L2224/4813 ,  H01L2224/48463 ,  H01L2224/4847 ,  H01L2224/48599 ,  H01L2224/49111 ,  H01L2224/49175 ,  H01L2924/00011 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01073 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/04941 ,  H01L2924/04953 ,  H01L2924/10253 ,  H01L2924/10271 ,  H01L2924/1033 ,  H01L2924/10335 ,  H01L2924/14 ,  H01L2924/20751 ,  Y10S977/762 ,  Y10S977/763 ,  Y10S977/811 ,  H01L2924/00014 ,  H01L2924/20651 ,  H01L2924/00 ,  H01L2924/01006

Abstract: Iridium oxide (IrOx) nanowires and a method forming the nanowires are provided. The method comprises: providing a growth promotion film with non-continuous surfaces, having a thickness in the range of 0.5 to 5 nanometers (nm), and made from a material such as Ti, Co, Ni, Au, Ta, polycrystalline silicon (poly-Si), SiGe, Pt, Ir, TiN, or TaN; establishing a substrate temperature in the range of 200 to 600 degrees C.; introducing oxygen as a precursor reaction gas; introducing a (methylcyclopentadienyl)(1,5-cyclooctadiene)iridium(I) precursor; using a metalorganic chemical vapor deposition (MOCVD) process, growing IrOx nanowires from the growth promotion film surfaces. The IrOx nanowires have a diameter in the range of 100 to 1000 Å, a length in the range of 1000 Å to 2 microns, an aspect ratio (length to width) of greater than 50:1. Further, the nanowires include single-crystal nanowire cores covered with an amorphous layer having a thickness of less than 10 Å.

Abstract translation: 提供氧化铱（IrOx）纳米线和形成纳米线的方法。 该方法包括：提供具有0.5至5纳米（nm）范围内的厚度的非连续表面的生长促进膜，并由诸如Ti，Co，Ni，Au，Ta，多晶硅 多晶硅），SiGe，Pt，Ir，TiN或TaN; 建立200〜600℃的基板温度。 引入氧气作为前体反应气体; 引入（甲基环戊二烯基）（1,5-环辛二烯）铱（I）前体; 使用金属有机化学气相沉积（MOCVD）工艺，从生长促进膜表面生长IrOx纳米线。 IrOx纳米线的直径在100至1000埃的范围内，长度在1000埃至2微米之间，纵横比（长宽比）大于50:1。 此外，纳米线包括覆盖有厚度小于Å的非晶层的单晶纳米线芯。

公开(公告)号：US20070167008A1

公开(公告)日：2007-07-19

申请号：US11717818

申请日：2007-03-14

Applicant: Sheng Hsu ,  Fengyan Zhang ,  Gregory Stecker ,  Robert Barrowcliff

Inventor： Sheng Hsu ,  Fengyan Zhang ,  Gregory Stecker ,  Robert Barrowcliff

IPC: H01L21/44

CPC classification number: H01L27/101 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/147 ,  H01L45/16 ,  H01L45/1675

Abstract: A non-volatile memory resistor cell with a nanotip electrode, and corresponding fabrication method are provided. The method comprises: forming a first electrode with nanotips; forming a memory resistor material adjacent the nanotips; and, forming a second electrode adjacent the memory resistor material, where the memory resistor material is interposed between the first and second electrodes. Typically, the nanotips are iridium oxide (IrOx) and have a tip base size of about 50 nanometers, or less, a tip height in the range of 5 to 50 nm, and a nanotip density of greater than 100 nanotips per square micrometer. In one aspect, the substrate material can be silicon, silicon oxide, silicon nitride, or a noble metal. A metalorganic chemical vapor deposition (MOCVD) process is used to deposit Ir. The IrOx nanotips are grown from the deposited Ir.

Abstract translation: 提供了具有纳米尖端电极的非易失性存储器电阻单元及相应的制造方法。 该方法包括：形成具有纳米尖端的第一电极; 在所述纳米尖端附近形成记忆电阻材料; 并且形成与所述存储电阻材料相邻的第二电极，其中所述存储电阻材料置于所述第一和第二电极之间。 通常，纳米针是氧化铱（IrOx），并且具有约50纳米或更小的尖端基底尺寸，在5至50nm范围内的尖端高度，以及每平方微米大于100纳米尖端的纳米密度密度。 一方面，衬底材料可以是硅，氧化硅，氮化硅或贵金属。 使用金属有机化学气相沉积（MOCVD）工艺沉积Ir。 IrOx纳米尖端从沉积的Ir生长。

公开(公告)号：US20070111368A1

公开(公告)日：2007-05-17

申请号：US11280423

申请日：2005-11-16

Applicant: Fengyan Zhang ,  Robert Barrowcliff ,  Sheng Hsu

Inventor： Fengyan Zhang ,  Robert Barrowcliff ,  Sheng Hsu

IPC: H01L51/40 ,  H01L21/00

CPC classification number: H01L51/4213 ,  B82Y10/00 ,  H01L51/0046 ,  H01L51/0048 ,  H01L51/4226 ,  H01L51/4233 ,  H01L51/441 ,  Y02E10/52 ,  Y02E10/549

Abstract: A photovoltaic (PV) structure is provided, along with a method for forming a PV structure with a conductive nanowire array electrode. The method comprises: forming a bottom electrode with conductive nanowires; forming a first semiconductor layer of a first dopant type (i.e., n-type) overlying the nanowires; forming a second semiconductor layer of a second dopant type, opposite of the first dopant type (i.e., p-type), overlying the first semiconductor layer; and, forming a top electrode overlying the second semiconductor layer. The first and second semiconductor layers can be a material such as a conductive polymer, a conjugated polymer with a fullerene derivative, and inorganic materials such as CdSe, CdS, Titania, or ZnO. The conductive nanowires can be a material such as IrO2, In2O3, SnO2, or indium tin oxide (ITO).

Abstract translation: 提供光伏（PV）结构以及用于形成具有导电纳米线阵列电极的PV结构的方法。 该方法包括：形成具有导电纳米线的底电极; 形成覆盖在纳米线上的第一掺杂剂型（即n型）的第一半导体层; 形成与所述第一掺杂剂类型（即，p型）相反的第二掺杂剂类型的第二半导体层，所述第二掺杂剂类型覆盖所述第一半导体层; 以及形成覆盖所述第二半导体层的顶部电极。 第一和第二半导体层可以是诸如导电聚合物，具有富勒烯衍生物的共轭聚合物和诸如CdSe，CdS，二氧化钛或ZnO的无机材料的材料。 导电纳米线可以是诸如IrO 2，In 2 O 3，SnO 2，或铟的材料 氧化锡（ITO）。

公开(公告)号：US07169637B2

公开(公告)日：2007-01-30

申请号：US10883228

申请日：2004-07-01

Applicant: Fengyan Zhang ,  Lisa H. Stecker ,  Bruce D. Ulrich ,  Sheng Teng Hsu

Inventor： Fengyan Zhang ,  Lisa H. Stecker ,  Bruce D. Ulrich ,  Sheng Teng Hsu

IPC: H01L21/06 ,  H01L21/461

CPC classification number: H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1675

Abstract: A one-mask etching method for use with a PCMO-containing RRAM to reduce stack side-wall residuals, includes preparing a substrate, taken from the group of substrates consisting of silicon, silicon dioxide and polysilicon; depositing a bottom electrode on the substrate; depositing a PCMO layer on the bottom electrode; depositing a top electrode on the PCMO layer; depositing a hard mask on the top electrode; depositing and patterning a photoresist layer on the hard mask; etching the hard mask; etching the top electrode using a first etching process having an etching atmosphere consisting of Ar, O2, and Cl2; etching the PCMO layer using an etching process taken from the group of etching processes consisting of the first etching process and a second etching process having an etching atmosphere consisting of Ar and O2. etching the bottom electrode using the first etching process; and completing the RRAM device.

Abstract translation: 包含含PCMO的RRAM以减少堆叠侧壁残留物的单掩模蚀刻方法包括制备从由硅，二氧化硅和多晶硅组成的一组衬底取得的衬底; 在底物上沉积底部电极; 在底部电极上沉​​积PCMO层; 在PCMO层上沉积顶部电极; 在顶部电极上沉​​积硬掩模; 在硬掩模上沉积和图案化光致抗蚀剂层; 蚀刻硬掩模; 使用具有由Ar，O 2和Cl 2组成的蚀刻气氛的第一蚀刻工艺蚀刻顶部电极; 使用从由第一蚀刻工艺和由Ar和O 2组成的蚀刻气氛的第二蚀刻工艺组成的蚀刻工艺组中的蚀刻工艺来蚀刻PCMO层。 使用第一蚀刻工艺蚀刻底部电极; 并完成RRAM设备。

公开(公告)号：US07141481B2

公开(公告)日：2006-11-28

申请号：US10909218

申请日：2004-07-29

Applicant: Sheng Teng Hsu ,  Wei-Wei Zhuang ,  Wei Pan ,  Fengyan Zhang

Inventor： Sheng Teng Hsu ,  Wei-Wei Zhuang ,  Wei Pan ,  Fengyan Zhang

IPC: H01L21/20

CPC classification number: G11C13/0007 ,  G11C2213/31 ,  G11C2213/77 ,  H01L27/2409 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1683

Abstract: A method of fabricating a nano-scale resistance cross-point memory array includes preparing a silicon substrate; depositing silicon oxide on the substrate to a predetermined thickness; forming a nano-scale trench in the silicon oxide; depositing a first connection line in the trench; depositing a memory resistor layer in the trench on the first connection line; depositing a second connection line in the trench on the memory resistor layer; and completing the memory array. A cross-point memory array includes a silicon substrate; a first connection line formed on the substrate; a colossal magnetoresistive layer formed on the first connection line; a silicon nitride layer formed on a portion of the colossal magnetoresistive layer; and a second connection line formed adjacent the silicon nitride layer and on the colossal magnetoresistive layer.

Abstract translation: 制造纳米尺度电阻交叉点存储器阵列的方法包括制备硅衬底; 在衬底上沉积氧化硅至预定厚度; 在氧化硅中形成纳米尺度的沟槽; 在沟槽中沉积第一连接线; 在第一连接线上的沟槽中沉积记忆电阻层; 在所述存储器电阻层的沟槽中沉积第二连接线; 并完成内存阵列。 交叉点存储器阵列包括硅衬底; 形成在所述基板上的第一连接线; 形成在第一连接线上的巨大的磁阻层; 形成在巨磁阻层的一部分上的氮化硅层; 以及与氮化硅层和巨磁阻层相邻形成的第二连接线。