公开(公告)号：US08497197B2

公开(公告)日：2013-07-30

申请号：US13061296

申请日：2010-09-26

申请人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

发明人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

IPC分类号： H01L21/3205

CPC分类号： H01L29/66545 ,  H01L21/26586 ,  H01L29/1083 ,  H01L29/51 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7847

摘要： A method for manufacturing a semiconductor structure includes providing an n-type field effect transistor comprising a source region, a drain region, and a first gate; forming a tensile stress layer on the n-type field effect transistor; removing the first gate so as to form a gate opening; performing an anneal so that the source region and the drain region memorize a stress induced by the tensile stress layer; forming a second gate; removing the tensile stress layer; and forming an interlayer dielectric layer on the n-type field effect transistor. A replacement process is combined with a stress memorization technique for enhancing the stress memorization effect and increasing mobility of electrons, which in turn improves overall properties of the semiconductor structure.

摘要翻译： 一种制造半导体结构的方法，包括提供包括源区，漏区和第一栅极的n型场效应晶体管; 在n型场效应晶体管上形成拉伸应力层; 移除第一门以形成门开口; 进行退火，使得源极区域和漏极区域记忆由拉伸应力层引起的应力; 形成第二个门; 去除拉应力层; 以及在n型场效应晶体管上形成层间电介质层。 替代过程与用于增强应力记忆效应和增加电子迁移率的应力记忆技术相结合，这又改善了半导体结构的整体性能。

公开(公告)号：US20130161642A1

公开(公告)日：2013-06-27

申请号：US13003873

申请日：2010-09-26

申请人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

发明人： Huilong Zhu ,  Zhijiong Luo ,  Haizhou Yin

IPC分类号： H01L29/78 ,  H01L29/66 ,  H01L29/788

CPC分类号： H01L29/785 ,  H01L21/26586 ,  H01L29/66636 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/7848

摘要： The present application discloses a semiconductor device and a method for manufacturing the same. The semiconductor device comprises an SOI substrate; a semiconductor fin formed on the SOI substrate, the semiconductor fin having a first side and a second side which are opposite to each other and stand upward on a surface of the SOI substrate, and a trench which is opened at a central portion of the second side and opposite to the first side; a channel region formed in the fin and being between the first side and the trench at the second side; source and drain regions formed in the fin and sandwiching the channel region; and a gate stack formed on the SOI substrate and being adjacent to the first side of the fin, wherein the gate stack comprises a first gate dielectric extending away from the first side and being adjacent to the channel region, a first conductor layer extending away from the first side and being adjacent to the first gate dielectric, a second gate dielectric extending away from the first side and being adjacent laterally to one side of the first conductor layer, and a second conductor layer extending away from the first side and being adjacent laterally to one side of the second gate dielectric. The embodiments of the invention can be applied in manufacturing an FinFET.

摘要翻译： 本申请公开了一种半导体器件及其制造方法。 半导体器件包括SOI衬底; 在所述SOI衬底上形成的半导体鳍片，所述半导体鳍片具有彼此相对并在所述SOI衬底的表面上向上并且在所述第二衬底的中心部分处开口的第一侧和第二侧; 侧和第一侧相对; 形成在所述翅片中并且在所述第二侧处在所述第一侧和所述沟槽之间的沟道区域; 源极和漏极区域形成在翅片中并夹着沟道区域; 以及形成在所述SOI衬底上并且邻近所述鳍的所述第一侧的栅极堆叠，其中所述栅极堆叠包括远离所述第一侧延伸并且邻近所述沟道区延伸的第一栅极电介质， 所述第一侧并且邻近所述第一栅极电介质延伸，所述第二栅极电介质延伸远离所述第一侧并且横向邻近所述第一导体层的一侧;以及第二导体层，所述第二导体层从所述第一侧延伸并且横向相邻 到第二栅极电介质的一侧。 本发明的实施例可以应用于制造FinFET。

公开(公告)号：US20130146977A1

公开(公告)日：2013-06-13

申请号：US13816227

申请日：2011-12-01

申请人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

发明人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

IPC分类号： H01L27/12 ,  H01L21/8238

CPC分类号： H01L27/1203 ,  H01L21/8238 ,  H01L29/66795 ,  H01L29/7846 ,  H01L29/785

摘要： The present invention discloses a semiconductor structure comprising: a semiconductor base located on an insulating layer, which is located on a semiconductor substrate; source/drain regions adjacent to opposite first sides of the semiconductor base; gates, positioned on a second set of two sides of the semiconductor base and said second set of two sides are opposite to each other; an insulating plug located on the insulating layer and embedded into the semiconductor base; and an epitaxial layer located between the insulating plug and the semiconductor base wherein the epitaxial layer is SiC for an NMOS device and the epitaxial layer is SiGe for a PMOS device. The present invention further discloses a method for manufacturing a semiconductor structure. The stress at the channel region is adjusted by forming a strained epitaxial layer, thus carrier mobility is improved and the performance of the semiconductor device is improved.

摘要翻译： 本发明公开了一种半导体结构，包括：位于绝缘层上的位于半导体衬底上的半导体基底; 源极/漏极区域与半导体基底的相对的第一侧相邻; 位于所述半导体基底的第二组两侧的所述第二组彼此相对; 位于所述绝缘层上且嵌入所述半导体基底中的绝缘插头; 以及位于绝缘插头和半导体基座之间的外延层，其中外延层是用于NMOS器件的SiC，外延层是用于PMOS器件的SiGe。 本发明还公开了半导体结构的制造方法。 通过形成应变外延层来调整沟道区的应力，从而提高载流子迁移率，提高半导体器件的性能。

公开(公告)号：US08441050B2

公开(公告)日：2013-05-14

申请号：US13077858

申请日：2011-03-31

申请人： Zhijiong Luo ,  Huilong Zhu ,  Haizhou Yin

发明人： Zhijiong Luo ,  Huilong Zhu ,  Haizhou Yin

IPC分类号： H01L29/76 ,  H01L27/12 ,  H01L21/336

CPC分类号： H01L29/7851 ,  H01L29/66795

摘要： A fin transistor structure and a method of fabricating the same are disclosed. In one aspect the method comprises providing a bulk semiconductor substrate, patterning the semiconductor substrate to form a fin with it body directly tied to the semiconductor substrate, patterning the fin so that gaps are formed on the bottom of the fin at source/drain regions of the transistor structure to be formed. This is performed wherein a portion of the fin corresponding to the channel region of the transistor structure to be formed is directly tied to the semiconductor substrate, while other portions of the fin at the source/drain regions are separated from the surface of the semiconductor substrate by the gaps. Also, filling an insulation material into the gaps, and fabricating the transistor structure based on the semiconductor substrate with the fin formed thereon are disclosed. Thereby, it is possible to reduce the leakage current while maintaining the advantages of body-tied structures.

摘要翻译： 公开了鳍式晶体管结构及其制造方法。 在一个方面，该方法包括提供体半导体衬底，图案化半导体衬底以形成鳍片，其主体直接连接到半导体衬底，图案化鳍片，使得在鳍片的底部形成间隙，在源极/漏极区域 要形成的晶体管结构。 这样做，其中对应于要形成的晶体管结构的沟道区的鳍的一部分直接连接到半导体衬底，而源极/漏极区的鳍的其它部分与半导体衬底的表面分离 由差距。 此外，公开了将绝缘材料填充到间隙中，并且制造基于其上形成有翅片的半导体衬底的晶体管结构。 因此，可以在保持身体结构的优点的同时减小漏电流。

公开(公告)号：US08440558B2

公开(公告)日：2013-05-14

申请号：US12991012

申请日：2010-09-16

申请人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

发明人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

IPC分类号： H01L29/772

CPC分类号： H01L29/66575 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/76897 ,  H01L23/485 ,  H01L29/66545

摘要： There is provided a semiconductor device and a method of fabricating the same. The method comprises: providing a semiconductor substrate; forming a transistor structure on the semiconductor substrate, wherein the transistor structure comprises a gate region and a source/drain region, and the gate region comprises a gate dielectric layer provided on the semiconductor substrate and a sacrificial gate formed on the gate dielectric layer; depositing a first interlayer dielectric layer, and planarizing the first interlayer dielectric layer to expose the sacrificial gate; removing the sacrificial gate to form a replacement gate hole; forming first contact holes at positions corresponding to the source/drain region in the first interlayer dielectric layer; and filling a first conductive material in the first contact holes and the replacement gate hole respectively to form first contacts and a replacement gate, wherein the first contacts come into contact with the source/drain region. Thereby, the replacement gate and the first contacts can be made in one same step of depositing the same material, and thus the process flows are simplified.

摘要翻译： 提供了一种半导体器件及其制造方法。 该方法包括：提供半导体衬底; 在所述半导体衬底上形成晶体管结构，其中所述晶体管结构包括栅极区域和源极/漏极区域，并且所述栅极区域包括设置在所述半导体衬底上的栅极介电层和形成在所述栅极电介质层上的牺牲栅极; 沉积第一层间介电层，平面化第一层间电介质层以暴露牺牲栅极; 去除牺牲栅极以形成替换门孔; 在与所述第一层间电介质层中的所述源极/漏极区对应的位置处形成第一接触孔; 以及分别在所述第一接触孔和所述替换栅极孔中填充第一导电材料以形成第一触点和替换栅极，其中所述第一触点与所述源极/漏极区域接触。 因此，可以在沉积相同材料的同一步骤中制造更换栅极和第一触点，从而简化了工艺流程。

公开(公告)号：US20130099361A1

公开(公告)日：2013-04-25

申请号：US13580965

申请日：2012-05-14

申请人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

发明人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

IPC分类号： H01L21/20 ,  H01L29/06

CPC分类号： H01L21/20 ,  H01L27/1211 ,  H01L29/0657 ,  H01L29/66795

摘要： The present invention provides a method for manufacturing a semiconductor structure, comprising the steps of: providing a semiconductor substrate, forming an insulating layer on the semiconductor substrate, and forming a semiconductor base layer on the insulating layer; forming a sacrificial layer and a spacer surrounding the sacrificial layer on the semiconductor base layer, and etching the semiconductor base layer by taking the spacer as a mask to form a semiconductor body; forming an insulating film on sidewalls of the semiconductor body; removing the sacrificial layer and the semiconductor body located under the sacrificial layer to form a first semiconductor fin and a second semiconductor fin. Correspondingly, the present invention further provides a semiconductor structure. In the present invention, an oxide film is formed on the sidewalls of the two semiconductor fins that are far away from each other, while only the sidewalls of the two semiconductor fins that are opposite to each other are exposed, such that conventional operations may be easily performed to the sidewalls opposite to each other in the subsequent process.

摘要翻译： 本发明提供一种制造半导体结构的方法，包括以下步骤：提供半导体衬底，在半导体衬底上形成绝缘层，并在绝缘层上形成半导体基底层; 在所述半导体基底层上形成包围所述牺牲层的牺牲层和间隔物，并且通过以所述间隔物作为掩模来蚀刻所述半导体基底层以形成半导体本体; 在半导体主体的侧壁上形成绝缘膜; 去除位于牺牲层下方的牺牲层和半导体本体以形成第一半导体鳍片和第二半导体鳍片。 相应地，本发明还提供一种半导体结构。 在本发明中，在远离彼此的两个半导体翅片的侧壁上形成氧化膜，只有两个相互相对的两个半导体翅片的侧壁露出，这样常规的操作可以是 在随后的过程中容易地对彼此相对的侧壁进行。

公开(公告)号：US08420490B2

公开(公告)日：2013-04-16

申请号：US12999086

申请日：2010-06-25

申请人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

发明人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

IPC分类号： H01L21/336

CPC分类号： H01L29/495 ,  H01L21/26513 ,  H01L21/2652 ,  H01L21/2658 ,  H01L21/26586 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66492 ,  H01L29/66545

摘要： The present invention relates to a method of manufacturing a semiconductor device, and the method uses the mode of thermal annealing the source/drain regions and performing Halo ion implantation to form a Halo ion-implanted region by: first removing the dummy gate to expose the gate dielectric layer to form an opening; then performing a tilted Halo ion implantation to the device from the opening to form a Halo ion-implanted region on both sides of the channel of the semiconductor device; and then annealing to activate the dopants in the Halo ion-implanted region; finally performing subsequent process to the device according to the requirement of the manufacture process. Through the present invention, the dopants in the Halo ion-implanted region improperly introduced to the source region and the drain region may be reduced, and then the overlap between the Halo ion-implantation region and the dopant region of the source/drain regions may be reduced, thus to reduce the band-band leakage current in the MOSFET, and hence improve the performance of the device.

摘要翻译： 本发明涉及一种制造半导体器件的方法，该方法使用对源/漏区进行热退火的方式，并进行Halo离子注入以形成Halo离子注入区域，方法是首先除去虚拟栅极以暴露出 栅介电层形成开口; 然后从所述开口对所述器件进行倾斜的Halo离子注入，以在所述半导体器件的沟道的两侧上形成Halo离子注入区域; 然后退火以激活卤素离子注入区域中的掺杂剂; 最后根据制造过程的要求对设备进行后续处理。 通过本发明，可以减少不适当地引入源极区域和漏极区域的卤素离子注入区域中的掺杂剂，然后卤素离子注入区域和源极/漏极区域的掺杂剂区域之间的重叠可以 减小，从而降低MOSFET中的带带漏电流，从而提高器件的性能。

公开(公告)号：US08415621B2

公开(公告)日：2013-04-09

申请号：US13381074

申请日：2011-07-22

申请人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

发明人： Haizhou Yin ,  Huilong Zhu ,  Zhijiong Luo

IPC分类号： G01B15/00

CPC分类号： G01B21/02 ,  G01B2210/56 ,  H01L22/12 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for line width measurement, comprising: providing a substrate, wherein a raised line pattern is formed on a surface of the substrate, and the line pattern has a width; forming a first measurement structure and a second measurement structure on opposite sidewalls of the line pattern in the width direction of the line pattern; removing the line pattern; and measuring the spacing between the first measurement structure and the second measurement structure, and obtaining the width of the line pattern by subtracting a predetermined offset from the spacing. The present invention facilitates to reduce the uncertainty associated with the measuring process and to improve the measurement precision.

摘要翻译： 一种线宽测量方法，包括：提供衬底，其中在所述衬底的表面上形成凸起线图案，并且所述线图案具有宽度; 在所述线条图案的宽度方向的相对侧壁上形成第一测量结构和第二测量结构; 去除线条图案; 并且测量第一测量结构和第二测量结构之间的间距，并且通过从该间隔减去预定的偏移来获得线图案的宽度。 本发明有助于减少与测量过程相关的不确定性并提高测量精度。

公开(公告)号：US20130049069A1

公开(公告)日：2013-02-28

申请号：US13577443

申请日：2011-11-25

申请人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

发明人： Huilong Zhu ,  Haizhou Yin ,  Zhijiong Luo

IPC分类号： H01L29/78 ,  H01L21/31 ,  H01L21/20

CPC分类号： H01L29/66795 ,  H01L29/1054 ,  H01L29/785

摘要： Semiconductor devices and methods for manufacturing the semiconductor devices are disclosed. A semiconductor device includes a substrate, a fin formed above the substrate with a semiconductor layer formed between the substrate and the fin, and a gate stack crossing over the fin. The fin and the semiconductor layer may include different materials and have etching selectivity with respect to each other. A patterning of the fin can be stopped reliably on the semiconductor layer. Therefore, it is possible to better control the height of the fin and thus the channel width of the final device.

摘要翻译： 公开了用于制造半导体器件的半导体器件和方法。 半导体器件包括衬底，在衬底上形成的鳍片，其具有形成在衬底和鳍片之间的半导体层，以及跨越鳍片的栅极堆叠。 翅片和半导体层可以包括不同的材料并且具有相对于彼此的蚀刻选择性。 可以在半导体层上可靠地停止翅片的图案化。 因此，可以更好地控制翅片的高度，从而更好地控制最终装置的通道宽度。

公开(公告)号：US20130040435A1

公开(公告)日：2013-02-14

申请号：US13377527

申请日：2011-08-09

申请人： Haizhou Yin ,  Zhijiong Luo ,  Huilong Zhu

发明人： Haizhou Yin ,  Zhijiong Luo ,  Huilong Zhu

IPC分类号： H01L21/336

CPC分类号： H01L29/66545 ,  H01L29/6659 ,  H01L29/7833

摘要： A method for manufacturing a transistor and a semiconductor device is provided. The method for manufacturing a transistor may comprise: defining an active area on a semiconductor substrate, and forming on the active area a gate stack or a dummy gate stack, a source/drain extension region, a spacer and a source/drain region, wherein the source/drain extension region is embedded in the active area and self-aligned on both sides of the gate stack or dummy gate stack, the spacer surrounds the gate stack or dummy gate stack, and the source/drain region is embedded in the active area and self-aligned outside the spacer; removing at least a portion of the spacer to expose a portion of the active area; and forming an interlayer dielectric layer which covers the gate stack or dummy gate stack, the spacer and the exposed active area, wherein the dielectric constant of the material of the interlayer dielectric layer is smaller than that of the removed material of the spacer. It is beneficial for reducing the capacitance between the gate region and the source/drain region as well as between the gate region and the contact plug.

摘要翻译： 提供一种制造晶体管和半导体器件的方法。 晶体管的制造方法可以包括：在半导体衬底上限定有源区，以及在有源区上形成栅极堆叠或虚设栅极堆叠，源极/漏极延伸区域，间隔物和源极/漏极区域，其中 源极/漏极延伸区域嵌入有源区域并在栅极堆叠或伪栅极堆叠的两侧自对准，间隔物围绕栅极堆叠或伪栅极堆叠，并且源极/漏极区域嵌入有源区域 区域和间隔物外自对准; 去除所述间隔物的至少一部分以暴露所述有效区域的一部分; 以及形成覆盖所述栅极堆叠或伪栅极堆叠，所述间隔物和所述暴露的有源区的层间电介质层，其中所述层间电介质层的材料的介电常数小于所述间隔物的去除材料的介电常数。 有利于减小栅极区域和源极/漏极区域之间以及栅极区域和接触插塞之间的电容。