公开(公告)号：US20050190612A1

公开(公告)日：2005-09-01

申请号：US11117479

申请日：2005-04-29

申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takeshi Sakata ,  Takao Watanabe

发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takeshi Sakata ,  Takao Watanabe

IPC分类号： G11C5/00 ,  H03K19/0185

CPC分类号： H03K19/0016 ,  H03K19/018521

摘要： A semiconductor device including a level converter (LSC) is disclosed. The level converter comprises a voltage-up circuit (LSC1) that operates on low voltage of power supply (VDD) and steps up voltage enough to drive the level converter and a level converter circuit (LSC2) that operates on high voltage of power supply (VDDQ). The voltage-up circuit is capable of constantly generating 2×VDD so that the level converter can convert a low voltage of power supply (VDD) below 1 V to VDDQ. This voltage-up circuit can be configured only with MOSFET transistors produced by thin oxide film deposition, thus enabling high-speed operation. To facilitate designing a circuit for preventing a leakage current from occurring in the level converter during sleep mode of a low-voltage-driven circuit (CB1), the level converter circuit (LSC2) includes a leak protection circuit (LPC) that exerts autonomous control for leak prevention, dispensing with external control signals.

摘要翻译： 公开了一种包括电平转换器（LSC）的半导体器件。 电平转换器包括在低电压（VDD）下工作并升压足以驱动电平转换器的升压电路（LSC 1）和在高电压功率下工作的电平转换器电路（LSC 2） 电源（VDDQ）。 升压电路能够持续产生2xVDD，因此电平转换器可将低于1 V的低电压电压（VDD）转换为VDDQ。 该升压电路只能由通过薄氧化膜沉积制造的MOSFET晶体管配置，从而实现高速操作。 为了便于设计用于防止低电压驱动电路（CB 1）的睡眠模式期间在电平转换器中发生漏电流的电路，电平转换器电路（LSC 2）包括泄漏保护电路（LPC） 自动控制防泄漏，外接控制信号。

公开(公告)号：US06933765B2

公开(公告)日：2005-08-23

申请号：US10149189

申请日：2000-12-21

申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takeshi Sakata ,  Takao Watanabe

发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takeshi Sakata ,  Takao Watanabe

IPC分类号： G11C5/00 ,  H03K19/0185 ,  H03L5/00

CPC分类号： H03K19/0016 ,  H03K19/018521

摘要： A semiconductor device including a level converter (LSC) is disclosed. The level converter comprises a voltage-up circuit (LSC1) that operates on low voltage of power supply (VDD) and steps up voltage enough to drive the level converter and a level converter circuit (LSC2) that operates on high voltage of power supply (VDDQ). The voltage-up circuit is capable of constantly generating 2×VDD so that the level converter can convert a low voltage of power supply (VDD) below 1 V to VDDQ. This voltage-up circuit can be configured only with MOSFET transistors produced by thin oxide film deposition, thus enabling high-speed operation. To facilitate designing a circuit for preventing a leakage current from occurring in the level converter during sleep mode of a low-voltage-driven circuit (CB1), the level converter circuit (LSC2) includes a leak protection circuit (LPC) that exerts autonomous control for leak prevention, dispensing with external control signals.

公开(公告)号：US06700429B2

公开(公告)日：2004-03-02

申请号：US10211565

申请日：2002-08-05

申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Kazumasa Yanagisawa

发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Kazumasa Yanagisawa

IPC分类号： H03L500

CPC分类号： H03K5/1534 ,  H03K3/356113 ,  H03K19/018521

摘要： A semiconductor device includes a differential level converter circuit that receives a first signal and outputs a second signal of greater amplitude. The differential level converter has a first MISFET pair for receiving the first signal, a second MISFET pair for enhancing the withstand voltage of the first MISFET pair, and a third MISFET pair with cross-coupled gates for latching the second signal from output. The film thickness of the gate insulating films of the second and third MISFET pairs is made thicker than that of the first MISFET pair, and the threshold voltages of the first and second MISFET pairs are made smaller than that of the third MISFET pair. This level converter circuit operates at high speed even if there is a large difference in the signal amplitude before and after level conversion.

公开(公告)号：US06687175B1

公开(公告)日：2004-02-03

申请号：US10149221

申请日：2002-06-10

申请人： Hiroyuki Mizuno ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

发明人： Hiroyuki Mizuno ,  Takeshi Sakata ,  Nobuhiro Oodaira ,  Takao Watanabe ,  Yusuke Kanno

IPC分类号： G11C700

CPC分类号： G11C11/4076 ,  G11C7/04 ,  G11C7/065 ,  G11C7/08 ,  G11C7/12 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C2207/002 ,  G11C2207/005

摘要： The present invention provides a sense circuit for DRAM memory cell to cover the events that a sense time becomes remarkably longer when a power source voltage is lowered, a sense time under the low voltage condition becomes shorter when temperature rises and a sense time changes to a large extent for fluctuation of processes. The present invention provides the following typical effects. A switch means is provided between the bit line BL and local bit line LBL connected to the memory cells for isolation and coupling of these bit lines. The bit line BL is precharged to the voltage of VDL/2, while the local bit line LBL is precharged to the voltage of VDL. The VDL is the maximum amplitude voltage of the bit line BL.

摘要翻译： 本发明提供了一种用于DRAM存储单元的感测电路，以覆盖当电源电压降低时感测时间变得显着更长的事件，当温度升高时，低电压条件下的感测时间变短，感测时间变为 过程波动很大程度。 本发明提供以下典型的效果。 在位线BL和连接到存储器单元的局部位线LBL之间提供开关装置，用于这些位线的隔离和耦合。 位线BL被预充电到VDL / 2的电压，而局部位线LBL被预充电到VDL的电压。 VDL是位线BL的最大幅度电压。

公开(公告)号：US06519195B2

公开(公告)日：2003-02-11

申请号：US09818509

申请日：2001-03-28

申请人： Yusuke Kanno ,  Kiyoo Itoh

发明人： Yusuke Kanno ,  Kiyoo Itoh

IPC分类号： G11C700

CPC分类号： G11C7/18 ,  G11C11/405 ,  G11C11/4097

摘要： A semiconductor integrated circuit is disclosed, in which a memory is activated at high speed in commensurate with a high-speed logic circuit mounted with the memory in order to reduce the cost using a DRAM of a 3-transistor cell requiring no capacitor. A pair of data lines connected with a plurality of memory cells having the amplification function are set to different precharge voltage values, thereby eliminating the need of a dummy cell. The elimination of the need of the dummy cell unlike in the conventional DRAM circuit using a gain cell reduces both the required space and the production cost. A hierarchical structure of the data lines makes a high-speed operation possible. Also, a DRAM circuit can be fabricated through a fabrication process matched with an ordinary logic element.

摘要翻译： 公开了一种半导体集成电路，其中存储器以与安装有存储器的高速逻辑电路相当的高速度被激活，以便使用不需要电容器的3晶体管单元的DRAM来降低成本。 与具有放大功能的多个存储单元连接的一对数据线被设置为不同的预充电电压值，从而不需要虚设单元。 与使用增益单元的常规DRAM电路不同，消除虚设电池的需要减少了所需空间和生产成本。 数据线的层次结构使得高速操作成为可能。 此外，可以通过与普通逻辑元件匹配的制造工艺来制造DRAM电路。

公开(公告)号：US06438641B1

公开(公告)日：2002-08-20

申请号：US09495954

申请日：2000-02-02

申请人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takao Watanabe

发明人： Yusuke Kanno ,  Hiroyuki Mizuno ,  Takao Watanabe

IPC分类号： G06F1212

CPC分类号： G06F12/0607 ,  G06F12/0882

摘要： In an information processing apparatus involving a cache accessed by INDEX and TAG addresses, accesses to the main memory include many accesses attributable to the local character of referencing and write-back accesses attributable to the replacement of cache contents. Accordingly, high speed accessing requires efficient assignment of the two kinds of accesses to banks of the DRAM. In assigning request addresses from the CPU to different banks of the DRAM, bank addresses of the DRAM and generated by operation of the INDEX field and the TAG field so that local accesses whose INDEX varies and accesses at the time of writing back of which INDEX remains the same but TAG differs can be assigned to different banks. High speed accessing is made possible because accesses to the main memory can be assigned to separate banks. Furthermore, as reading and writing at the time of writing back can be assigned to a separate bank, pseudo dual-port accessing is made possible with only one port, resulting in higher speed write-back accessing.

摘要翻译： 在涉及由INDEX和TAG地址访问的高速缓冲存储器的信息处理装置中，对主存储器的访问包括归因于替代缓存内容的引用和回写访问的本地字符的许多访问。 因此，高速存取需要对DRAM的存储体的两种访问进行有效的分配。 在将请求地址从CPU分配给DRAM的不同组时，DRAM的存储区地址并通过INDEX字段和TAG字段的操作生成，以便INDEX在写入INDEX时保留的本地访问变化并访问 相同但TAG不同可以分配给不同的银行。 高速访问是可能的，因为可以将主存储器的访问分配给单独的存储区。 此外，由于在回写时的读写可以分配给单独的存储区，因此只能使用一个端口进行伪双端口访问，从而实现更高速的写回访问。