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189 条记录 (耗时 0.05 秒)

    System, method and computer program product for providing a programmable quiesce filtering register
    93.
    发明授权
    System, method and computer program product for providing a programmable quiesce filtering register 失效
    用于提供可编程静态滤波寄存器的系统，方法和计算机程序产品

    公开(公告)号：US08140834B2

    公开(公告)日：2012-03-20

    申请号：US12037808

    申请日：2008-02-26

    申请人： Lisa C. Heller ,  Harald Boehm ,  Ute Gaertner ,  Jennifer A. Navarro ,  Timothy J. Slegel

    发明人： Lisa C. Heller ,  Harald Boehm ,  Ute Gaertner ,  Jennifer A. Navarro ,  Timothy J. Slegel

    IPC分类号： G06F9/48 ,  G06F9/52

    CPC分类号： G06F9/4812

    摘要： A system, method and computer program product for providing a programmable quiesce filtering register. The method includes receiving a quiesce interruption request at the processor. The processor is executing in a mode. A filtering zone associated with the mode is identified. It is determined if the quiesce interruption request can be filtered by the processor. The determining is responsive to the filtering zone and to contents of a programmable filtering register for indicating exceptions to filtering performed by the receiving processor. The quiesce interruption request is filtered in response to determining that the request can be filtered.

    摘要翻译： 一种用于提供可编程静态滤波寄存器的系统，方法和计算机程序产品。 该方法包括在处理器处接收静止中断请求。 处理器正在以一种模式执行。 识别与该模式相关联的过滤区域。 确定处理器是否可以过滤停顿中断请求。 该确定响应于过滤区域和可编程过滤寄存器的内容，用于指示接收处理器执行的过滤异常。 响应于确定可以对请求进行过滤，过滤掉静默中断请求。

    Extract cache attribute facility and instruction therefore
    94.
    发明授权
    Extract cache attribute facility and instruction therefore 有权
    因此提取缓存属性设备和指令

    公开(公告)号：US08131934B2

    公开(公告)日：2012-03-06

    申请号：US12966316

    申请日：2010-12-13

    申请人： Dan F. Greiner ,  Timothy J. Slegel

    发明人： Dan F. Greiner ,  Timothy J. Slegel

    IPC分类号： G06F13/00

    CPC分类号： G06F9/30145 ,  G06F9/30047 ,  G06F9/30058 ,  G06F9/30167 ,  G06F9/322

    摘要： A facility and cache machine instruction of a computer architecture for specifying a target cache cache-level and a target cache attribute of interest for obtaining a cache attribute of one or more target caches. The requested cache attribute of the target cache(s) is saved in a register.

    摘要翻译： 一种用于指定目标缓存高速缓存级别和感兴趣的目标高速缓存属性的用于获得一个或多个目标高速缓存的高速缓存属性的计算机体系结构的设施和缓存机器指令。 所请求的高速缓存属性被保存在一个寄存器中。

    Dynamic address translation with DAT protection
    96.
    发明授权
    Dynamic address translation with DAT protection 有权
    动态地址转换与DAT保护

    公开(公告)号：US08019964B2

    公开(公告)日：2011-09-13

    申请号：US11972715

    申请日：2008-01-11

    申请人： Dan F. Greiner ,  Charles W. Gainey, Jr. ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Charles F. Webb

    发明人： Dan F. Greiner ,  Charles W. Gainey, Jr. ,  Lisa C. Heller ,  Damian L. Osisek ,  Erwin Pfeffer ,  Timothy J. Slegel ,  Charles F. Webb

    IPC分类号： G06F12/16

    CPC分类号： G06F12/1009 ,  G06F12/145 ,  G06F2212/651 ,  G06F2212/652

    摘要： What is provided is an enhanced dynamic address translation facility. In one embodiment, a virtual address to be translated and an initial origin address of any one of a region first table, a region second table, a region third table, or a segment table are obtained. Based on the obtained initial origin address, a segment table entry is obtained which contains a format control and DAT protection fields. If the format control field is enabled, obtaining from the translation table entry a segment-frame absolute address of a large block of data in main storage. The segment-frame absolute address is combined with a page index portion and a byte index portion of the virtual address to form a translated address of the desired block of data. If the DAT protection field is not enabled, fetches and stores are permitted to the desired block of data addressed by the translated virtual address.

    摘要翻译： 提供的是增强的动态地址转换设施。 在一个实施例中，获得要转换的虚拟地址和区域第一表，区域秒表，区域第三表或段表中的任何一个的初始起始地址。 基于获得的初始起始地址，获得包含格式控制和DAT保护字段的段表条目。 如果格式控制字段被使能，则从转换表条目获得主存储器中的大块数据的段帧绝对地址。 分段帧绝对地址与虚拟地址的页索引部分和字节索引部分组合，以形成所需数据块的转换地址。 如果DAT保护字段未被使能，则获取和存储被允许被转换的虚拟地址寻址的所需数据块。

    Rotate then operate on selected bits facility and instructions therefore
    97.
    发明授权
    Rotate then operate on selected bits facility and instructions therefore 有权
    然后旋转然后对选定的位设备和指令进行操作

    公开(公告)号：US07895419B2

    公开(公告)日：2011-02-22

    申请号：US11972679

    申请日：2008-01-11

    申请人： Dan F. Greiner ,  Timothy J. Slegel ,  Joachim von Buttlar

    发明人： Dan F. Greiner ,  Timothy J. Slegel ,  Joachim von Buttlar

    IPC分类号： G06F9/30 ,  G06F9/35

    CPC分类号： G06F9/30029 ,  G06F9/30032 ,  G06F9/30145 ,  G06F9/30167 ,  G06F9/30185 ,  G06F9/30189 ,  G06F9/342

    摘要： A rotate then operate instruction having a T bit is fetched and executed wherein a first operand in a first register is rotated by an amount and a Boolean operation is performed on a selected portion of the rotated first operand and a second operand in of a second register. If the T bit is ‘0’ the selected portion of the result of the Boolean operation is inserted into corresponding bits of a second operand of a second register. If the T bit is ‘1’, in addition to the inserted bits, the bits other than the selected portion of the rotated first operand are saved in the second register.

    摘要翻译： 旋转，然后操作具有T位的指令被执行，其中第一寄存器中的第一操作数旋转一个量，并且对旋转的第一操作数的选定部分执行布尔运算，并且在第二寄存器中执行第二操作数 。 如果T位为“0”，则将布尔运算结果的选定部分插入到第二寄存器的第二个操作数的相应位中。 如果T位为“1”，除了插入的位之外，所转动的第一个操作数的选定部分以外的其他位被保存在第二个寄存器中。

    Register indirect access of program floating point registers by millicode
    99.
    发明授权
    Register indirect access of program floating point registers by millicode 失效
    通过millicode寄存器间接访问程序浮点寄存器

    公开(公告)号：US07712076B2

    公开(公告)日：2010-05-04

    申请号：US11531301

    申请日：2006-09-13

    申请人： Steven R. Carlough ,  Mark S. Farrell ,  Eric M. Schwarz ,  Timothy J. Slegel ,  Charles F. Webb

    发明人： Steven R. Carlough ,  Mark S. Farrell ,  Eric M. Schwarz ,  Timothy J. Slegel ,  Charles F. Webb

    IPC分类号： G06F9/44

    CPC分类号： G06F9/3017 ,  G06F9/35

    摘要： Complex floating point instructions are executed under millicode control when it is not cost effective to implement its function in hardware. One of the disadvantages to executing complex instructions using millicode routines is that determining and accessing the instructions operands are costly for millicode performance. To determine what the source and target location are, the instruction text is parsed. Furthermore the millicode instruction stream must be modified to access the operand data from and write the result to the program registers specified by the complex floating point instruction. The invention overcomes these disadvantages by providing millicode with register indirect access to the program floating point registers.

    摘要翻译： 当在硬件中实现其功能不具有成本效益时，复杂的浮点指令在毫秒控制下执行。 使用millicode例程执行复杂指令的一个缺点是确定和访问指令操作数对于millicode性能来说是昂贵的。 要确定源和目标位置是什么，解释说明文本。 此外，必须修改millicode指令流以访问操作数数据，并将结果写入由复杂浮点指令指定的程序寄存器。 本发明通过向编程浮点寄存器提供寄存器间接访问的毫代码来克服这些缺点。

    METHOD, SYSTEM, COMPUTER PROGRAM PRODUCT, AND HARDWARE PRODUCT FOR IMPLEMENTING RESULT FORWARDING BETWEEN DIFFERENTLY SIZED OPERANDS IN A SUPERSCALAR PROCESSOR
    100.
    发明申请
    METHOD, SYSTEM, COMPUTER PROGRAM PRODUCT, AND HARDWARE PRODUCT FOR IMPLEMENTING RESULT FORWARDING BETWEEN DIFFERENTLY SIZED OPERANDS IN A SUPERSCALAR PROCESSOR 失效
    方法，系统，计算机程序产品和用于在超级处理器中执行不同尺寸操作之前的结果的硬件产品

    公开(公告)号：US20090240922A1

    公开(公告)日：2009-09-24

    申请号：US12051792

    申请日：2008-03-19

    申请人： David S. Hutton ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  Christopher A. Krygowski ,  Edward T. Malley ,  Jeffrey S. Plate ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum ,  Timothy J. Slegel

    发明人： David S. Hutton ,  Fadi Y. Busaba ,  Bruce C. Giamei ,  Christopher A. Krygowski ,  Edward T. Malley ,  Jeffrey S. Plate ,  John G. Rell, JR. ,  Chung-Lung Kevin Shum ,  Timothy J. Slegel

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3016 ,  G06F9/30036 ,  G06F9/3828

    摘要： Result and operand forwarding is provided between differently sized operands in a superscalar processor by grouping a first set of instructions for operand forwarding, and grouping a second set of instructions for result forwarding, the first set of instructions comprising a first source instruction having a first operand and a first dependent instruction having a second operand, the first dependent instruction depending from the first source instruction; the second set of instructions comprising a second source instruction having a third operand and a second dependent instruction having a fourth operand, the second dependent instruction depending from the second source instruction, performing operand forwarding by forwarding the first operand, either whole or in part, as it is being read to the first dependent instruction prior to execution; performing result forwarding by forwarding a result of the second source instruction, either whole or in part, to the second dependent instruction, after execution; wherein the operand forwarding is performed by executing the first source instruction together with the first dependent instruction; and wherein the result forwarding is performed by executing the second source instruction together with the second dependent instruction.

    摘要翻译： 通过对用于操作数转发的第一组指令进行分组，以及对用于结果转发的第二组指令进行分组，在超标量处理器中的不同大小的操作数之间提供结果和操作数转发，所述第一组指令包括具有第一操作数的第一源指令 以及具有第二操作数的第一依赖指令，所述第一依赖指令取决于所述第一源指令; 所述第二组指令包括具有第三操作数和第二从属指令的第二源指令，所述第三操作数和第二从属指令具有第四操作数，所述第二依赖指令取决于所述第二源指令，通过转发所述第一操作数全部或部分地执行操作数转发， 因为它在执行之前被读取到第一个依赖指令; 执行结果转发，将第二源指令的结果全部或部分转发到第二依赖指令; 其中通过与第一依赖指令一起执行第一源指令来执行操作数转发; 并且其中通过与第二从属指令一起执行第二源指令来执行结果转发。