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91.发明授权Data processing system and method for efficient communication utilizing an Ig coherency state 失效数据处理系统和利用Ig一致性状态的高效通信方法公开(公告)号：US07584329B2
公开(公告)日：2009-09-01
申请号：US11055524
申请日：2005-02-10
IPC分类号： G06F12/00
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit and a cache memory. The cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is possibly cached outside of the first coherency domain.
摘要翻译： 高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元和高速缓冲存储器。 高速缓存存储器包括高速缓存控制器，包括用于高速缓存存储器块的数据存储位置的数据阵列和高速缓存目录。 缓存目录包括用于存储与存储器块相关联的地址标签的标签字段和与标签字段和数据存储位置相关联的一致性状态字段。 一致性状态字段具有多个可能的状态，包括指示地址标签有效的状态，存储位置不包含有效数据，并且存储器块可能被高速缓存在第一相干域之外。
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92.发明申请CACHE MECHANISM AND METHOD FOR AVOIDING CAST OUT ON BAD VICTIM SELECT AND RECYCLING VICTIM SELECT OPERATION 有权高速缓存机制和方法，用于避免在BAD VICTIM SELECT和RECYCLING VICTIM选择操作公开(公告)号：US20090150617A1
公开(公告)日：2009-06-11
申请号：US11951783
申请日：2007-12-06
IPC分类号： G06F12/08
CPC分类号： G06F12/126 , G06F12/125 , G06F2212/1032
摘要： A method, apparatus, and computer for identifying selection of a bad victim during victim selection at a cache and recovering from such bad victim selection without causing the system to crash or suspend forward progress of the victim selection process. Among the bad victim selection addressed are recovery from selection of a deleted member and recovery from use of LRU state bits that do not map to a member within the congruence class. When LRU victim selection logic generates an output vector identifying a victim, the output vector is checked to ensure that it is a valid vector (non-null) and that it is not pointing to a deleted member. When the output vector is not valid or points to a deleted member, the LRU victim selection logic is triggered to re-start the victim selection process.
摘要翻译： 一种方法，装置和计算机，用于在高速缓存的受害者选择期间识别对不良受害者的选择，并从这种不良受害者选择中恢复，而不会导致系统崩溃或中止向前进行受害者选择过程。 所解决的不良受害者选择之一是从选择已删除成员的恢复以及使用不映射到同余类中的成员的LRU状态位进行恢复。 当LRU受害者选择逻辑生成识别受害者的输出向量时，检查输出向量以确保它是有效向量（非空值），并且不指向已删除的成员。 当输出向量无效或指向被删除成员时，LRU受害者选择逻辑被触发以重新启动受害者选择过程。
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93.发明授权公开(公告)号：US07490200B2
公开(公告)日：2009-02-10
申请号：US11054924
申请日：2005-02-10
IPC分类号： G06F12/08
CPC分类号： G06F12/0851 , G06F12/0811
摘要： A cache memory logically partitions a cache array having a single access/command port into at least two slices, and uses a first cache directory to access the first cache array slice while using a second cache directory to access the second cache array slice, but accesses from the cache directories are managed using a single cache arbiter which controls the single access/command port. In the illustrative embodiment, each cache directory has its own directory arbiter to handle conflicting internal requests, and the directory arbiters communicate with the cache arbiter. An address tag associated with a load request is transmitted from the processor core with a designated bit that associates the address tag with only one of the cache array slices whose corresponding directory determines whether the address tag matches a currently valid cache entry. The cache array may be arranged with rows and columns of cache sectors wherein a given cache line is spread across sectors in different rows and columns, with at least one portion of the given cache line being located in a first column having a first latency and another portion of the given cache line being located in a second column having a second latency greater than the first latency. The cache array outputs different sectors of the given cache line in successive clock cycles based on the latency of a given sector.
摘要翻译： 高速缓存存储器将具有单个访问/命令端口的高速缓存阵列逻辑地分割成至少两个切片，并且使用第一高速缓存目录访问第一高速缓存阵列切片，同时使用第二高速缓存目录来访问第二高速缓存阵列切片，但是访问 从缓存目录中使用单个缓存仲裁器来管理单个访问/命令端口。 在说明性实施例中，每个高速缓存目录具有其自己的目录仲裁器来处理冲突的内部请求，并且目录仲裁器与缓存仲裁器通信。 与处理器核心相关联的地址标签被从处理器核心以指定的位发送，指定的位将地址标签与只有一个高速缓存阵列片相关联，其相应的目录确定地址标签是否与当前有效的高速缓存条目匹配。 高速缓存阵列可以布置有高速缓存扇区的行和列，其中给定的高速缓存行分布在不同行和列中的扇区之间，其中给定高速缓存行的至少一部分位于具有第一等待时间的第一列和另一个 给定高速缓存行的一部分位于具有大于第一等待时间的第二等待时间的第二列中。 缓存阵列基于给定扇区的等待时间在连续的时钟周期中输出给定高速缓存行的不同扇区。
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公开(公告)号：US20080177953A1
公开(公告)日：2008-07-24
申请号：US11951770
申请日：2007-12-06
IPC分类号： G06F12/12
CPC分类号： G06F12/126 , G06F12/0897 , G06F12/123 , G06F12/128
摘要： A method and apparatus for enabling protection of a particular member of a cache during LRU victim selection. LRU state array includes additional “protection” bits in addition to the state bits. The protection bits serve as a pointer to identify the location of the member of the congruence class that is to be protected. A protected member is not removed from the cache during standard LRU victim selection, unless that member is invalid. The protection bits are pipelined to MRU update logic, where they are used to generate an MRU vector. The particular member identified by the MRU vector (and pointer) is protected from selection as the next LRU victim, unless the member is Invalid. The make MRU operation affects only the lower level LRU state bits arranged a tree-based structure and thus only negates the selection of the protected member, without affecting LRU victim selection of the other members.
摘要翻译： 一种用于在LRU受害者选择期间能够保护缓存的特定成员的方法和装置。 LRU状态阵列除了状态位之外还包括额外的“保护”位。 保护位用作用于标识要保护的同余类的成员的位置的指针。 在标准LRU受害者选择期间，保护成员不会从缓存中删除，除非该成员无效。 保护位被流水线到MRU更新逻辑，它们用于生成MRU向量。 由MRU向量（和指针）标识的特定成员不被选择作为下一个LRU受害者，除非成员无效。 使MRU操作仅影响布置了基于树的结构的较低级LRU状态位，并且因此仅在不影响其他成员的LRU受害者选择的情况下否定对被保护成员的选择。
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95.发明授权Pipelining D states for MRU steerage during MRU/LRU member allocation 失效在MRU / LRU成员分配过程中，管理MRU操纵的D状态公开(公告)号：US07401189B2
公开(公告)日：2008-07-15
申请号：US11054067
申请日：2005-02-09
CPC分类号： G06F12/0888 , G06F12/123 , G06F12/126 , G06F2212/1032
摘要： A method and apparatus for preventing selection of Deleted (D) members as an LRU victim during LRU victim selection. During each cache access targeting the particular congruence class, the deleted cache line is identified from information in the cache directory. A location of a deleted cache line is pipelined through the cache architecture during LRU victim selection. The information is latched and then passed to MRU vector generation logic. An MRU vector is generated and passed to the MRU update logic, which is selects/tags the deleted member as a MRU member. The make MRU operation affects only the lower level LRU state bits arranged in a tree-based structure state bits so that the make MRU operation only negates selection of the specific member in the D state, without affecting LRU victim selection of the other members.
摘要翻译： 用于在LRU受害者选择期间防止选择被删除（D）成员作为LRU受害者的方法和装置。 在针对特定同余类的每个缓存访问期间，从高速缓存目录中的信息识别已删除的高速缓存行。 删除的高速缓存行的位置在LRU受害者选择期间通过高速缓存架构流水线化。 信息被锁存，然后传递给MRU向量生成逻辑。 生成MRU向量并将其传递给MRU更新逻辑，MRU更新逻辑是将删除的成员作为MRU成员进行选择/标记。 使MRU操作仅影响以基于树的结构状态位布置的较低级LRU状态位，使得MRU操作仅在D状态下否定特定成员的选择，而不影响其他成员的LRU受害者选择。
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96.发明授权Half-good mode for large L2 cache array topology with different latency domains 有权具有不同延迟域的大型L2缓存阵列拓扑的半好模式公开(公告)号：US07308537B2
公开(公告)日：2007-12-11
申请号：US11055262
申请日：2005-02-10
CPC分类号： G06F12/0851 , G06F12/126
摘要： A cache memory logically partitions a cache array into at least two slices each having a plurality of cache lines, with a given cache line spread across two or more cache ways of contiguous bytes and a given cache way shared between the two cache slices, and if one a cache way is defective that is part of a first cache line in the first cache slice and part of a second cache line in the second cache slice, it is disabled while continuing to use at least one other cache way which is also part of the first cache line and part of the second cache line. In the illustrative embodiment the cache array is set associative and at least two different cache ways for a given cache line contain different congruence classes for that cache line. The defective cache way can be disabled by preventing an eviction mechanism from allocating any congruence class in the defective way. For example, half of the cache line can be disabled (i.e., half of the congruence classes). The cache array may be arranged with rows and columns of cache sectors (rows corresponding to the cache ways) wherein a given cache line is further spread across sectors in different rows and columns, with at least one portion of the given cache line being located in a first column having a first latency and another portion of the given cache line being located in a second column having a second latency greater than the first latency. The cache array can also output different sectors of the given cache line in successive clock cycles based on the latency of a given sector.
摘要翻译： 高速缓存存储器将高速缓存阵列逻辑地分区成至少两个切片，每个切片具有多个高速缓存行，其中给定的高速缓存行分布在连续字节的两个或多个高速缓存路径上以及在两个高速缓存片之间共享的给定高速缓存路径，如果 一个缓存方式是缺陷，其是第一高速缓存片中的第一高速缓存行和第二高速缓存片中的第二高速缓存行的一部分的一部分，其被禁用，同时继续使用至少另一种其他缓存方式，其也是 第一个缓存行和第二个缓存行的一部分。 在说明性实施例中，高速缓存阵列被设置为关联性，并且给定高速缓存行的至少两个不同的高速缓存路径包含该高速缓存行的不同的一致类。 可以通过防止驱逐机制以有缺陷的方式分配任何一致类来禁用缺陷缓存方式。 例如，可以禁用一半的高速缓存行（即，一致等级的一半）。 高速缓存阵列可以被布置成具有行和列的高速缓存扇区（对应于高速缓存路线的行），其中给定高速缓存行进一步分布在不同行和列中的扇区之间，其中给定高速缓存行的至少一部分位于 具有第一延迟的第一列和给定高速缓存行的另一部分位于具有大于第一等待时间的第二等待时间的第二列中。 缓存阵列还可以基于给定扇区的等待时间在连续的时钟周期中输出给定高速缓存行的不同扇区。
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公开(公告)号：US07272664B2
公开(公告)日：2007-09-18
申请号：US10313330
申请日：2002-12-05
IPC分类号： G06F15/16 , G06F15/167 , G06F15/00 , G06F15/76
CPC分类号： G06F9/4812 , G06F9/30116 , G06F9/3017 , G06F9/3836 , G06F9/384 , G06F9/3857
摘要： A method and system are disclosed for managing saved process states in a memory of a data processing system that has multiple partitions executing independent operating systems. A hypervisor manager affords access to any processor in the data processing system for the purpose of storing process states for that processor to the memory, independent of the operating system running on the processor.
摘要翻译： 公开了一种用于管理具有执行独立操作系统的多个分区的数据处理系统的存储器中的保存的处理状态的方法和系统。 虚拟机管理程序管理器访问数据处理系统中的任何处理器，用于将处理器的处理状态存储到存储器中，而与处理器上运行的操作系统无关。
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98.发明授权Processor virtualization mechanism via an enhanced restoration of hard architected states 失效处理器虚拟化机制通过增强硬件架构状态的恢复公开(公告)号：US06981083B2
公开(公告)日：2005-12-27
申请号：US10313320
申请日：2002-12-05
CPC分类号： G06F9/30116 , G06F9/462
摘要： A method and system are disclosed for pre-loading a hard architected state of a next process from a pool of idle processes awaiting execution. When an executing process is interrupted on the processor, a hard architected state, which has been pre-stored in the processor, of a next process is loaded into architected storage locations in the processor. The next process to be executed, and thus its corresponding hard architected state that is pre-stored in the processor, are determined based on priorities assigned to the waiting processes.
摘要翻译： 公开了一种用于从等待执行的空闲进程池预加载下一个进程的硬结构状态的方法和系统。 当执行过程在处理器上中断时，下一个进程已被预先存储在处理器中的硬设计状态被加载到处理器中的架构存储位置。 基于分配给等待处理的优先级来确定要执行的下一个进程，并因此其预先存储在处理器中的相应的硬设计状态。
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99.发明授权Method and system for managing speculative requests in a multi-level memory hierarchy 失效用于管理多层内存层次结构中的推测性请求的方法和系统公开(公告)号：US06418516B1
公开(公告)日：2002-07-09
申请号：US09364409
申请日：1999-07-30
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1208
CPC分类号： G06F9/30047 , G06F9/3804 , G06F9/383 , G06F9/3842 , G06F12/0862 , G06F12/0897
摘要： A method of operating a multi-level memory hierarchy of a computer system and apparatus embodying the method, wherein instructions issue having an explicit prefetch request directly from an instruction sequence unit to a prefetch unit of the processing unit. The invention applies to values that are either operand data or instructions and treats instructions in a different manner when they are loaded speculatively. These prefetch requests can be demand load requests, where the processing unit will need the operand data or instructions, or speculative load requests, where the processing unit may or may not need the operand data or instructions, but a branch prediction or stream association predicts that they might be needed. The load requests are sent to the lower level cache when the upper level cache does not contain the value required by the load. If a speculative request is for an instruction which is likewise not present in the lower level cache, that request is ignored, keeping both the lower level and upper level caches free of speculative values that are infrequently used. If the value is present in the lower level cache, it is loaded into the upper level cache. If a speculative request is for operand data, the value is loaded only into the lower level cache if it is not already present, keeping the upper level cache free of speculative operand data.
摘要翻译： 一种操作计算机系统的多级存储器层级的方法和体现该方法的装置，其中指令从直接从指令序列单元向处理单元的预取单元发出具有显式预取请求的指令。 本发明适用于作为操作数数据或指令的值，并且当它们被推测地加载时以不同的方式对待指令。 这些预取请求可以是需求负载请求，其中处理单元将需要操作数数据或指令或推测性负载请求，其中处理单元可能需要或可能不需要操作数数据或指令，但分支预测或流关联预测 他们可能需要。 当高级缓存不包含负载所需的值时，负载请求将发送到较低级别的缓存。 如果对低级缓存中同样不存在的指令进行推测性请求，则忽略该请求，同时保持较低级别和上级缓存都不会被不经常使用的推测值。 如果该值存在于较低级缓存中，则将其加载到上级缓存中。 如果对于操作数数据是推测性请求，则该值仅在尚未存在的情况下被加载到较低级别的高速缓存中，保持高级缓存没有推测操作数数据。
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100.发明授权Data processing system and method for efficient coherency communication utilizing coherency domains 失效数据处理系统和方法，利用一致性域进行有效的一致性通信公开(公告)号：US08214600B2
公开(公告)日：2012-07-03
申请号：US11055402
申请日：2005-02-10
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/0817 , G06F12/0831
摘要： In a cache coherent data processing system including at least first and second coherency domains, a master performs a first broadcast of an operation within the cache coherent data processing system that is limited in scope of transmission to the first coherency domain. The master receives a response of the first coherency domain to the first broadcast of the operation. If the response indicates the operation cannot be serviced in the first coherency domain alone, the master increases the scope of transmission by performing a second broadcast of the operation in both the first and second coherency domains. If the response indicates the operation can be serviced in the first coherency domain, the master refrains from performing the second broadcast.
摘要翻译： 在包括至少第一和第二相干域的高速缓存相干数据处理系统中，主器件在高速缓存相干数据处理系统内进行第一广播，其被限制在传输范围到第一相干域。 主机接收第一个一致性域的响应到该操作的第一次广播。 如果响应指示仅在第一个相干域中不能进行操作，则主设备通过在第一和第二相干域中执行操作的第二次广播来增加传输的范围。 如果响应指示可以在第一相干域中服务操作，则主机不执行第二广播。
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