公开(公告)号：US20230082248A1

公开(公告)日：2023-03-16

申请号：US17477205

申请日：2021-09-16

Applicant: MACRONIX International Co., Ltd.

Inventor： Teng-Hao Yeh

IPC: G11C16/08 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11556 ,  H01L27/11526 ,  H01L27/11582 ,  H01L27/11573

Abstract: A three dimension memory device including a plurality of word lines, a plurality of first switches, a plurality of second switches and N conductive wire layers is provided, where N is a positive integer larger than 1. The word lines are divided into a plurality of word line groups. The first switches receive a common word line voltage. The second switches receive a reference ground voltage. A first word line group is connected to a first conductive wire layer through a second conductive wire layer. An ith word line group is connected to the first conductive wire layer through an (i+1)th to the second conductive wire layer in sequence.

公开(公告)号：US11309028B2

公开(公告)日：2022-04-19

申请号：US17011039

申请日：2020-09-03

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Po-Kai Hsu ,  Teng-Hao Yeh

IPC: G11C16/04 ,  G11C16/08 ,  G06N5/04 ,  G11C16/26 ,  G06F7/544 ,  G11C16/24

Abstract: An inference operation method and a controlling circuit of a 3D NAND artificial intelligence accelerator are provided. The 3D NAND artificial intelligence accelerator includes a plurality of memory cells, a plurality of bit lines, a plurality of word lines and a plurality of string selecting line groups each of which includes at least one string selecting line. The inference operation method includes the following steps: The patterns are inputted to the bit lines. The word lines are switched to switch the filters. The string selecting line groups are switched to switch the filters. In a word line pioneering scheme and a string selecting line group pioneering scheme, when the patterns inputted to each of the bit lines are switched, any one of the word lines is not switched and any one of the string selecting line groups is not switched.

公开(公告)号：US11221827B1

公开(公告)日：2022-01-11

申请号：US17006493

申请日：2020-08-28

Applicant: MACRONIX International Co., Ltd.

Inventor： Po-Kai Hsu ,  Teng-Hao Yeh ,  Tzu-Hsuan Hsu ,  Hang-Ting Lue

IPC: G06F7/544 ,  G06G7/16 ,  G06G7/14 ,  G06F7/501

Abstract: An in-memory computation device including a memory array, p×q analog to digital converters (ADCs) and a ladder adder is provided. The memory array is divided into p×q memory tiles, where p and q are positive integers larger than 1. Each of the memory tiles has a plurality local bit lines coupled to a global bit line respectively through a plurality of bit line selection switches. The bit line selection switches are turned on or cur off according to a plurality of control signals. The memory array receives a plurality of input signals. The ADCs are respectively coupled to a plurality of global bit lines of the memory tiles. The ADCs respectively convert electrical signals on the global bit lines to generate a plurality of sub-output signals. The ladder adder is coupled to the ADCs, and performs an addition operation on the sub-output signals to generate a calculation result.

公开(公告)号：US11183511B2

公开(公告)日：2021-11-23

申请号：US16257165

申请日：2019-01-25

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh

IPC: H01L27/115 ,  H01L27/105 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11565 ,  H01L21/28

Abstract: A memory device and a manufacturing method for the same are provided. The memory device comprises a stack structure and a channel structure. The stack structure is on a substrate and comprises gate electrodes and insulating films stacked alternately. The channel structure is electrically coupled to the gate electrodes, and is on sidewall surfaces of the gate electrodes. The channel structure comprises a first channel structure and a second channel structure. The second channel structure is on an upper surface of the first channel structure. The first channel structure and/or the second channel structure has a ring shape.

公开(公告)号：US20210241080A1

公开(公告)日：2021-08-05

申请号：US16782972

申请日：2020-02-05

Applicant: MACRONIX International Co., Ltd.

Inventor： HANG-TING LUE ,  Teng-Hao Yeh ,  Po-Kai Hsu ,  Ming-Liang Wei

IPC: G06N3/063 ,  G06F7/50 ,  G06F5/01 ,  G06F9/50

Abstract: An artificial intelligence accelerator receives a binary input data set and a selected layer of layers of overall weight pattern. The artificial intelligence accelerator includes processing tiles and a summation output circuit. Each processing tile receives one of input data subsets of the input data set and performs a convolution operation on weight blocks of each sub weight pattern of the overall weight pattern to obtain weight operation values and then obtains a weight output value expected from a direct convolution operation on the input data subset with the sub weight pattern through performing a multistage shifting and adding operation on the weight operation values. The summation output circuit sums up the plurality of weight output values through a multistage shifting and adding operation, so as to obtain a sum value expected from a direct convolution operation performed on the input data set with the overall weight pattern.

公开(公告)号：US10755790B2

公开(公告)日：2020-08-25

申请号：US16254933

申请日：2019-01-23

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao Yeh ,  Yi Ching Liu

IPC: G11C16/06 ,  G11C16/24 ,  H03K19/20 ,  G11C16/30 ,  G11C16/04 ,  G11C11/56

Abstract: A memory device is described with NAND strings and corresponding BL connected to SSL, a first power supply circuit, a second power supply circuit to distribute a higher supply voltage than the first power supply circuit, and a page buffer that generates program/inhibit outputs having a level between the first power supply voltage and a first reference voltage. Data line drivers drive nodes coupled to corresponding BL with a first voltage or a second voltage between the second power supply voltage and a second reference voltage. A data line driver includes a first switch transistor connected between the data line node and the second power supply circuit, a second switch transistor between the data line node and the second voltage reference, and a boost circuit to boost the gate of the first switch transistor above the first supply voltage level to turn on the first switch transistor.

公开(公告)号：US20200098774A1

公开(公告)日：2020-03-26

申请号：US16142901

申请日：2018-09-26

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue

IPC: H01L27/11565 ,  H01L27/1157 ,  H01L27/11582

Abstract: A memory device comprises a stack of conductive strips separated by insulating strips, the conductive strips in the stack extending in a first direction. The memory device comprises a plurality of hemi-cylindrical vertical channel structures extending through the conductive strips in the stack, each of the hemi-cylindrical vertical channel structures having a divided elliptical cross section with a major axis tilted relative to the first direction. The memory device comprises data storage structures on the sidewalls of the conductive strips. The hemi-cylindrical vertical channel structures comprise semiconductor films having outside surfaces in contact with the data storage structures on the sidewalls of the conductive strips.

公开(公告)号：US10593697B1

公开(公告)日：2020-03-17

申请号：US16540275

申请日：2019-08-14

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Chih-Wei Hu ,  Teng-Hao Yeh ,  Yu-Wei Jiang ,  Kuo-Pin Chang

IPC: H01L27/11582 ,  H01L27/1157

Abstract: A memory device includes a channel element, a gate electrode layer and a memory element. The channel element has a U shape. The gate electrode layer is electrically coupled to the channel element. The memory element surrounds a sidewall channel surface of the channel element.

公开(公告)号：US10566348B1

公开(公告)日：2020-02-18

申请号：US16180970

申请日：2018-11-05

Applicant: MACRONIX INTERNATIONAL CO., LTD.

Inventor： Teng-Hao Yeh ,  Hang-Ting Lue

IPC: H01L29/792 ,  H01L27/11582 ,  H01L29/10 ,  H01L23/528 ,  H01L21/8234

Abstract: A memory device comprises a reference conductor, and a stack of conductive strips separated by insulating strips, where the conductive strips in the stack extend in a first direction, and the stack is disposed on the reference conductor. The memory device comprises a plurality of hemi-cylindrical vertical channel structures extending through respective vias in the conductive strips in the stack, and comprising semiconductor films in electrical contact with the reference conductor having outside surfaces. Each of the hemi-cylindrical vertical channel structures has a divided elliptical cross section with a major axis tilted relative to the first direction. The memory device comprises data storage structures between the outside surfaces of the semiconductor films and sidewalls of the vias in the conductive strips.

公开(公告)号：US10535673B2

公开(公告)日：2020-01-14

申请号：US15996617

申请日：2018-06-04

Applicant: Macronix International Co., Ltd.

Inventor： Teng-Hao Yeh ,  Chih-Wei Hu ,  Hang-Ting Lue

IPC: H01L27/11 ,  H01L27/11556 ,  G11C16/10 ,  H01L27/11524 ,  H01L27/1157 ,  H01L27/11582 ,  H01L27/11565 ,  G11C16/04 ,  G11C11/56 ,  H01L27/11519

Abstract: A memory device that includes: a memory controller; a control unit; and a memory cell array that includes memory blocks, each memory block comprising: memory cells, word lines respectively coupled to the memory cells, signal lines to transfer signals to perform programming operations to one or more memory cells of the memory cells, a first metal layer coupled to a first group of lines and configured to route the first group of the lines to the control unit, the lines comprising the word lines and the signal lines, and a second metal layer coupled to a second group of the lines and configured to route the second group of the lines to the control unit, wherein the memory controller is configured to: control the control unit to (i) select particular memory cells and (ii) program data to the particular memory cells is disclosed.