公开(公告)号：US08188530B2

公开(公告)日：2012-05-29

申请号：US12728727

申请日：2010-03-22

申请人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Hiroyasu Tanaka ,  Ryota Katsumata ,  Hideaki Aochi ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： H01L21/8239 ,  H01L29/78 ,  H01L27/088

CPC分类号： H01L27/11578 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： A semiconductor memory device provided with a cell array section and a peripheral circuit section, the device includes: a back gate electrode; a stacked body provided on the back gate electrode; a plurality of semiconductor pillars extending in a stacking direction; connection members, each of the connection members connecting one of the semiconductor pillars to another one of the semiconductor pillars; a back-gate electrode contact applying a potential to the back gate electrode; a gate electrode provided in the peripheral circuit section; and a gate electrode contact applying a potential to the gate electrode, the back gate electrode and the gate electrode respectively including: a lower semiconductor layer; a conductive layer provided on the lower semiconductor layer; and an upper semiconductor layer provided on the conductive layer, the connection members being provided in or on the upper semiconductor layer, the back-gate electrode contact and the gate electrode contact being in contact with the conductive layer.

摘要翻译： 一种设置有单元阵列部分和外围电路部分的半导体存储器件，该器件包括：背栅电极; 设置在所述背栅电极上的层叠体; 沿层叠方向延伸的多个半导体柱; 连接构件，每个连接构件将半导体柱之一连接到另一个半导体柱; 向所述背栅电极施加电位的背栅极电极接触; 设置在所述外围电路部中的栅电极; 以及向所述栅电极，所述背栅电极和所述栅电极施加电位的栅电极接触部，分别包括：下半导体层; 设置在下半导体层上的导电层; 以及设置在所述导电层上的上半导体层，所述连接构件设置在所述上​​半导体层中或所述上半导体层上，所述背栅电极接触和所述栅电极接触与所述导电层接触。

公开(公告)号：US08148769B2

公开(公告)日：2012-04-03

申请号：US12534576

申请日：2009-08-03

申请人： Masaru Kito ,  Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi

发明人： Masaru Kito ,  Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi

IPC分类号： H01L29/788

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device includes a plurality of memory strings, each of which has a plurality of electrically rewritable memory cells connected in series; and select transistors, one of which is connected to each of ends of each of the memory strings. Each of the memory strings is provided with a first semiconductor layer having a pair of columnar portions extending in a perpendicular direction with respect to a substrate, and a joining portion formed so as to join lower ends of the pair of columnar portions; a charge storage layer formed so as to surround a side surface of the columnar portions; and a first conductive layer formed so as to surround the side surface of the columnar portions and the charge storage layer, and configured to function as a control electrode of the memory cells. Each of the select transistors is provided with a second semiconductor layer extending upwardly from an upper surface of the columnar portions; and a second conductive layer formed so as to surround a side surface of the second semiconductor layer with a gap interposed, and configured to function as a control electrode of the select transistors.

摘要翻译： 非易失性半导体存储器件包括多个存储串，每个存储串具有串联连接的多个电可重写存储单元; 并选择晶体管，其中一个连接到每个存储器串的每一端。 每个存储器串都具有第一半导体层，该第一半导体层具有相对于衬底在垂直方向上延伸的一对柱状部分，以及形成为连接该一对柱状部分的下端的接合部分; 形成为围绕所述柱状部的侧面的电荷存储层; 以及形成为围绕柱状部分的侧面和电荷存储层的第一导电层，并且被配置为用作存储单元的控制电极。 每个选择晶体管设置有从柱状部分的上表面向上延伸的第二半导体层; 以及第二导电层，其被形成为以间隔开的方式围绕所述第二半导体层的侧表面，并且被配置为用作所述选择晶体管的控制电极。

公开(公告)号：US20110233644A1

公开(公告)日：2011-09-29

申请号：US12839895

申请日：2010-07-20

申请人： Yoshiaki FUKUZUMI ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Hideaki Aochi

发明人： Yoshiaki FUKUZUMI ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Hideaki Aochi

IPC分类号： H01L29/792

CPC分类号： H01L29/7926 ,  H01L21/28282 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/42344 ,  H01L29/66833

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes first and second stacked structural bodies, first and second semiconductor pillars, a memory unit connection portion, a selection unit stacked structural body, first and second selection unit semiconductor pillars, a selection unit connection portion, and first to fifth interconnections. The semiconductor pillars pierce the stacked structural bodies. The first and second interconnections are connected to the first and second semiconductor pillars, respectively. The memory unit connection portion connects the first and second semiconductor pillars. The selection unit semiconductor pillars pierce the selection unit stacked structural body. The third and fourth interconnections are connected to the first and second selection unit semiconductor pillars, respectively. The selection unit connection portion connects the first and second selection unit semiconductor pillars. The fifth interconnection is connected to the third interconnection on a side opposite to the selection unit stacked structural body.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括第一和第二堆叠结构体，第一和第二半导体柱，存储单元连接部分，选择单元堆叠结构体，第一和第二选择单元半导体柱，选择单元连接部分 ，以及第一至第五互连。 半导体支柱刺穿堆叠的结构体。 第一和第二互连分别连接到第一和第二半导体柱。 存储单元连接部分连接第一和第二半导体柱。 选择单元半导体柱刺穿选择单元堆叠结构体。 第三和第四互连分别连接到第一和第二选择单元半导体柱。 选择单元连接部分连接第一和第二选择单元半导体柱。 第五互连在与选择单元堆叠结构体相反的一侧连接到第三互连。

公开(公告)号：US07969789B2

公开(公告)日：2011-06-28

申请号：US12536226

申请日：2009-08-05

申请人： Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi

发明人： Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Yosuke Komori ,  Hideaki Aochi

IPC分类号： G11C16/04

CPC分类号： H01L27/11578 ,  G11C11/5671 ,  G11C16/0475 ,  G11C16/0483 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11582

摘要： In a nonvolatile semiconductor memory device having n (n is an integer of two or more) electrode films stacked and having charge storage layers provided above and below each of the electrode films, when data “0” is written by injecting electrons into the charge storage layer on a source line side of a memory cell of the number k (k is an integer of 1 to (n−1)) as counted from an end on a bit line side in a selected semiconductor pillar, positive program potential is given to the electrode film of the number 1 to k as counted from the bit line side, and 0 V is given to the electrode film of the number (k+1) to n, therewith positive potential is given to the bit line and 0 V is given to the source line.

摘要翻译： 在具有n（n为2以上的整数）的电极膜的非易失性半导体存储装置中，在各电极膜的上下配置有电荷存储层的情况下，在将数据“0”注入到电荷存储部 在选择的半导体柱中从位线侧的端部开始计数k（k为1〜（n-1）的整数）的存储单元的源极侧的层，将正的程序电位赋予 从位线侧计数1〜k的电极膜，向数字（k + 1）〜n的电极膜施加0V，其中给定位线为0V，0V为 给源线。

公开(公告)号：US20110075481A1

公开(公告)日：2011-03-31

申请号：US12694677

申请日：2010-01-27

申请人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Tomoko Fujiwara ,  Megumi Ishiduki ,  Yosuke Komori ,  Yoshimasa Mikajiri ,  Shigeto Oota ,  Ryouhei Kirisawa ,  Hideaki Aochi

发明人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Tomoko Fujiwara ,  Megumi Ishiduki ,  Yosuke Komori ,  Yoshimasa Mikajiri ,  Shigeto Oota ,  Ryouhei Kirisawa ,  Hideaki Aochi

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C11/34 ,  G11C5/02 ,  G11C16/26

摘要： A nonvolatile semiconductor memory device comprises: a bit line; a source line; a memory string having a plurality of electrically data-rewritable memory transistors connected in series; a first select transistor provided between one end of the memory string and the bit line; a second select transistor provided between the other end of the memory string and the source line; and a control circuit configured to control a read operation. A plurality of the memory strings connected to one bit line via a plurality of the first select transistors. During reading of data from a selected one of the memory strings, the control circuit renders conductive the first select transistor connected to an unselected one of the memory strings and renders non-conductive the second select transistor connected to unselected one of the memory strings.

摘要翻译： 非易失性半导体存储器件包括：位线; 源线; 具有串联连接的多个电数据可重写存储晶体管的存储器串; 设置在存储器串的一端和位线之间的第一选择晶体管; 设置在存储器串的另一端与源极线之间的第二选择晶体管; 以及控制电路，被配置为控制读取操作。 经由多个第一选择晶体管连接到一个位线的多个存储器串。 在从选择的一个存储器串读取数据期间，控制电路使连接到未选择的一个存储器串的第一选择晶体管导通，并且使第二选择晶体管连接到未选择的一个存储器串。

公开(公告)号：US20110049608A1

公开(公告)日：2011-03-03

申请号：US12723981

申请日：2010-03-15

申请人： Masaru KIDOH ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Masaru KIDOH ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L29/66833 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

摘要： A memory string comprises: a first semiconductor layer including a columnar portion extending in a stacking direction on a substrate; a first charge storage layer surrounding the columnar portion; and a plurality of first conductive layers stacked on the substrate so as to surround the first charge storage layer. A select transistor comprises: a second semiconductor layer in contact with an upper surface of the columnar portion and extending in the stacking direction; a second charge storage layer surrounding the second semiconductor layer; and a second conductive layer deposited above the first conductive layer to surround the second charge storage layer. The second charge storage layer is formed from a layer downward of the second conductive layer to an upper end vicinity of the second conductive layer, and is not formed in a layer upward of the upper end vicinity.

摘要翻译： 存储器串包括：第一半导体层，包括在基板上沿堆叠方向延伸的柱状部分; 围绕所述柱状部分的第一电荷存储层; 以及堆叠在所述基板上以围绕所述第一电荷存储层的多个第一导电层。 选择晶体管包括：与柱状部分的上表面接触并沿堆叠方向延伸的第二半导体层; 围绕所述第二半导体层的第二电荷存储层; 以及沉积在所述第一导电层上方以围绕所述第二电荷存储层的第二导电层。 第二电荷存储层由第二导电层向下的层向第二导电层的上端附近形成，并且不形成在上端附近的上方。

公开(公告)号：US20110013454A1

公开(公告)日：2011-01-20

申请号：US12726858

申请日：2010-03-18

申请人： Tomoo Hishida ,  Yoshihisa Iwata ,  Megumi Ishiduki ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhel Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Tomoo Hishida ,  Yoshihisa Iwata ,  Megumi Ishiduki ,  Ryota Katsumata ,  Yoshiaki Fukuzumi ,  Masaru Kito ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Junya Matsunami ,  Tomoko Fujiwara ,  Hideaki Aochi ,  Ryouhel Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： G11C16/04 ,  G11C11/34

CPC分类号： G11C5/025 ,  G11C5/02 ,  G11C5/04 ,  G11C16/0483 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582

摘要： A nonvolatile semiconductor memory device comprises: a plurality of first memory strings; a first select transistor having one end thereof connected to one end of the first memory strings; a first line commonly connected to the other end of a plurality of the first select transistors; a switch circuit having one end thereof connected to the first line; and a second line commonly connected to the other end of a plurality of the switch circuits. The switch circuit controls electrical connection between the second line and the first line.

摘要翻译： 非易失性半导体存储器件包括：多个第一存储器串; 第一选择晶体管，其一端连接到第一存储器串的一端; 通常连接到多个第一选择晶体管的另一端的第一线; 开关电路，其一端连接到第一线; 以及通常连接到多个开关电路的另一端的第二线。 开关电路控制第二线和第一线之间的电连接。

公开(公告)号：US20100207195A1

公开(公告)日：2010-08-19

申请号：US12679991

申请日：2008-12-09

申请人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi

发明人： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi

IPC分类号： H01L29/792 ,  H01L21/336

CPC分类号： H01L27/11582 ,  G11C16/0483 ,  H01L27/1052 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11578 ,  H01L29/513

摘要： A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers functions as gate electrodes of the memory cells.

摘要翻译： 非挥发性半导体存储装置具有多个存储串，其中多个电可重写存储单元串联连接。 每个存储串包括第一半导体层，每个第一半导体层具有相对于衬底在垂直方向上延伸的一对柱状部分和形成为耦合该对柱状部分的下端的耦合部分; 形成为围绕所述柱状部的侧面的电荷存储层; 以及形成为围绕柱状部分和电荷存储层的侧表面的第一导电层。 第一导电层用作存储器单元的栅电极。

公开(公告)号：US20100109072A1

公开(公告)日：2010-05-06

申请号：US12563832

申请日：2009-09-21

申请人： Masaru KIDOH ,  Hiroyasu Tanaka ,  Ryota Katsumata ,  Masaru Kito ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi ,  Yoshiaki Fukuzumi

发明人： Masaru KIDOH ,  Hiroyasu Tanaka ,  Ryota Katsumata ,  Masaru Kito ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi ,  Yoshiaki Fukuzumi

IPC分类号： H01L27/115 ,  H01L21/8246

CPC分类号： H01L27/11578 ,  H01L21/76816 ,  H01L27/0688 ,  H01L27/112 ,  H01L27/11582

摘要： A nonvolatile semiconductor memory device includes a first stacked body on a silicon substrate, and a second stacked body is provided thereon. The first stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films, and a first portion of a through-hole extending in a stacking direction is formed. The second stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films, and a second portion of the through-hole is formed. A memory film is formed on an inner face of the through-hole, and a silicon pillar is buried in an interior of the through-hole. A central axis of the second portion of the through-hole is shifted from a central axis of the first portion, and a lower end of the second portion is positioned lower than an upper portion of the first portion.

摘要翻译： 非易失性半导体存储器件包括在硅衬底上的第一层叠体，并且在其上设置第二层叠体。 第一堆叠体包括交替层叠有多个电极膜的多个绝缘膜，并且形成沿堆叠方向延伸的通孔的第一部分。 第二堆叠体包括交替层叠有多个电极膜的多个绝缘膜，并且形成通孔的第二部分。 在通孔的内表面上形成记忆膜，并且将硅柱埋在通孔的内部。 通孔的第二部分的中心轴线从第一部分的中心轴线偏移，并且第二部分的下端位于比第一部分的上部更低的位置。

公开(公告)号：US08884355B2

公开(公告)日：2014-11-11

申请号：US12727712

申请日：2010-03-19

申请人： Yosuke Komori ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

发明人： Yosuke Komori ,  Hideaki Aochi ,  Ryota Katsumata ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Megumi Ishiduki ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC分类号： H01L29/72 ,  H01L29/792 ,  H01L27/115 ,  H01L29/66

CPC分类号： H01L29/792 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device includes: a stacked structural unit including a plurality of electrode films and a plurality of inter-electrode insulating films alternately stacked in a first direction; a first selection gate electrode stacked on the stacked structural unit in the first direction; a first semiconductor pillar piercing the stacked structural unit and the first selection gate electrode in the first direction; a first memory unit provided at an intersection of each of the electrode films and the first semiconductor pillar; and a first selection gate insulating film provided between the first semiconductor pillar and the first selection gate electrode, the first selection gate electrode including a first silicide layer provided on a face of the first selection gate electrode perpendicular to the first direction.

摘要翻译： 非易失性半导体存储器件包括：堆叠结构单元，包括多个电极膜和沿第一方向交替堆叠的多个电极间绝缘膜; 第一选择栅电极，沿第一方向堆叠在层叠结构单元上; 第一半导体柱在第一方向上穿透层叠结构单元和第一选择栅电极; 设置在每个电极膜和第一半导体柱的交点处的第一存储单元; 以及设置在所述第一半导体柱和所述第一选择栅极之间的第一选择栅极绝缘膜，所述第一选择栅电极包括设置在所述第一选择栅电极的与所述第一方向垂直的面上的第一硅化物层。