利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

163 条记录 (耗时 0.083 秒)

    PORTABLE ELECTRONIC DEVICE
    97.
    发明申请
    PORTABLE ELECTRONIC DEVICE 失效
    便携式电子设备

    公开(公告)号：US20100038916A1

    公开(公告)日：2010-02-18

    申请号：US12447085

    申请日：2007-08-30

    申请人： Tomonari Yomoda ,  Toshio Yoshida

    发明人： Tomonari Yomoda ,  Toshio Yoshida

    IPC分类号： F02B63/04

    CPC分类号： H02J7/32 ,  H04M1/021 ,  H04M1/21 ,  Y02B40/90

    摘要： There is provided a portable electronic device capable of being immediately operated without the use of a battery even when the battery reaches exhaustion. An electricity generating unit 131 is embedded in the portable electronic device. The electricity generating unit 131 has a mechanism to pull out a pull line 113 wound around a pulley 135 to wind up a spiral spring 133 and a mechanism to transfer torque occurring when the spiral spring 133 is released and to rotate the motor at high speed. An output voltage from the motor 142 is adjusted and smoothed by a constant voltage circuit and is directly supplied as power to power consuming components. The portable electronic device connecting two flips can wind up the spiral spring 133 by opening and closing the two flips.

    摘要翻译： 提供了即使在电池耗尽时也能立即使用电池而不使用电池的便携式电子设备。 发电单元131嵌入在便携式电子设备中。 发电单元131具有拉出缠绕在滑轮135上的拉线113以卷起螺旋弹簧133的机构，以及用于传递当螺旋弹簧133被释放时发生的扭矩并且使马达高速旋转的机构。 来自电动机142的输出电压由恒定电压电路调节和平滑，并且直接作为功率供应给功率消耗部件。 连接两个翻转件的便携式电子设备可以通过打开和关闭两个翻转来卷起螺旋弹簧133。

    Processor for executing instruction control in accordance with dynamic pipeline scheduling and a method thereof
    98.
    发明授权
    Processor for executing instruction control in accordance with dynamic pipeline scheduling and a method thereof 有权
    用于根据动态流水线调度执行指令控制的处理器及其方法

    公开(公告)号：US07337304B2

    公开(公告)日：2008-02-26

    申请号：US10349085

    申请日：2003-01-23

    申请人： Toshio Yoshida

    发明人： Toshio Yoshida

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3836 ,  G06F9/384 ,  G06F9/3857

    摘要： When all of a plurality of instructions are symmetry instructions, a symmetry instruction issuing unit issues the symmetry instructions to a plurality of reservation stations provided for every different arithmetic operating units until they become full. If it is determined that there is an asymmetry instruction among the plurality of instructions and the residual instructions are the symmetry instructions, an asymmetry instruction issuing unit 56 develops the asymmetry instruction into a multiflow of a previous flow and a following flow, issues the asymmetry instruction to the reservation station provided in correspondence to the specific arithmetic operating unit, and issues the residual symmetry instructions to the plurality of reservation stations provided for every different arithmetic operating units in an issuing cycle different from that of the asymmetry instruction until they become full.

    摘要翻译： 当所有多个指令都是对称指令时，对称指令发布单元向对每个不同的算术运算单元提供的多个保留​​站发出对称指令，直到它们变为满。 如果确定在多个指令中存在不对称指令，并且残留指令是对称指令，则不对称指令发布单元56将不对称指令展开为先前流程和随后流程的多个指令，发出不对称指令 发送到与特定算术运算单元相对应地设置的保留站，并且以与不对称指令不同的发布周期向每个不同算术运算单元提供的多个保留​​站发出剩余对称指令，直到它们变满为止。

    Multithread processor and thread switching control method
    99.
    发明授权
    Multithread processor and thread switching control method 有权
    多线程处理器和线程切换控制方式

    公开(公告)号：US07310705B2

    公开(公告)日：2007-12-18

    申请号：US10981772

    申请日：2004-11-05

    申请人： Toshio Yoshida ,  Masaki Ukai ,  Naohiro Kiyota

    发明人： Toshio Yoshida ,  Masaki Ukai ,  Naohiro Kiyota

    IPC分类号： G06F12/08 ,  G06F12/12 ,  G06F12/10

    CPC分类号： G06F12/0859 ,  G06F9/3824 ,  G06F9/3851 ,  G06F12/0811 ,  G06F12/0842

    摘要： The present invention relates to a multithread processor. In the multithread processor, when a cache miss occurs on a request related to an instruction in, of a plurality of caches arranged hierarchically, a cache at the lowest place in the hierarchy, with respect to the request suffering the cache miss, a cache control unit notifies an instruction identifier and a thread identifier, which are related to the instruction, to a multithread control unit. When a cache miss occurs on an instruction to be next completed, the multithread control unit makes the switching between threads on the basis of the instruction identifier and thread identifier notified from the cache control unit. This enables effective thread switching, thus enhancing the processing speed.

    摘要翻译： 多线程处理器技术领域本发明涉及一种多线程处理器。 在多线程处理器中，当在与分级排列的多个高速缓存中的指令相关的请求上发生高速缓存未命中时，相对于遭受高速缓存未命中的请求，层级中的最低位置处的高速缓存，高速缓存控制 单元将与指令相关的指令标识符和线程标识符通知给多线程控制单元。 当在接下来完成的指令上发生高速缓存未命中时，多线程控制单元基于从缓存控制单元通知的指令标识符和线程标识符进行线程之间的切换。 这使得能够有效的线程切换，从而提高处理速度。

    Processor and instruction control method
    100.
    发明授权
    Processor and instruction control method 有权
    处理器和指令控制方法

    公开(公告)号：US07287150B2

    公开(公告)日：2007-10-23

    申请号：US10347337

    申请日：2003-01-21

    申请人： Toshio Yoshida

    发明人： Toshio Yoshida

    IPC分类号： G06F9/30

    CPC分类号： G06F9/3826 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3857

    摘要： When a predetermined instruction is fetched and decoded, an instruction issuing unit develops the instruction operation into a multiflow of a previous flow and a following flow and issues the instruction by in-order. It is held into a reservation station. An instruction executing unit executes the instruction held in the reservation station by out-of-order. Further, an execution result of the instruction is committed by in-order. A multiflow guarantee processing unit guarantees an execution result of the previous flow stored in an allocation register on a register update buffer until the following flow is committed. Even if the previous flow is committed and the allocation register is released, the guaranteeing process is realized by stalling another instruction serving as a next register allocation destination in a decoding cycle until the following flow is committed.

    摘要翻译： 当预取指令被取出并解码时，指令发布单元将指令操作开发成先前流程和后续流程的多个流程，并按顺序发出指令。 它被放在一个保留站。 指令执行单元通过无序执行在保留站中保存的指令。 此外，指令的执行结果按顺序进行。 多保证处理单元保证存储在寄存器更新缓冲器中的分配寄存器中的先前流程的执行结果，直到下一个流程被提交。 即使先前的流程被提交并且分配寄存器被释放，通过在解码周期中停止作为下一个寄存器分配目的地的另一个指令来实现保证过程，直到下一个流程被提交。