公开(公告)号：US07310705B2

公开(公告)日：2007-12-18

申请号：US10981772

申请日：2004-11-05

申请人： Toshio Yoshida ,  Masaki Ukai ,  Naohiro Kiyota

发明人： Toshio Yoshida ,  Masaki Ukai ,  Naohiro Kiyota

IPC分类号： G06F12/08 ,  G06F12/12 ,  G06F12/10

CPC分类号： G06F12/0859 ,  G06F9/3824 ,  G06F9/3851 ,  G06F12/0811 ,  G06F12/0842

摘要： The present invention relates to a multithread processor. In the multithread processor, when a cache miss occurs on a request related to an instruction in, of a plurality of caches arranged hierarchically, a cache at the lowest place in the hierarchy, with respect to the request suffering the cache miss, a cache control unit notifies an instruction identifier and a thread identifier, which are related to the instruction, to a multithread control unit. When a cache miss occurs on an instruction to be next completed, the multithread control unit makes the switching between threads on the basis of the instruction identifier and thread identifier notified from the cache control unit. This enables effective thread switching, thus enhancing the processing speed.

摘要翻译： 多线程处理器技术领域本发明涉及一种多线程处理器。 在多线程处理器中，当在与分级排列的多个高速缓存中的指令相关的请求上发生高速缓存未命中时，相对于遭受高速缓存未命中的请求，层级中的最低位置处的高速缓存，高速缓存控制 单元将与指令相关的指令标识符和线程标识符通知给多线程控制单元。 当在接下来完成的指令上发生高速缓存未命中时，多线程控制单元基于从缓存控制单元通知的指令标识符和线程标识符进行线程之间的切换。 这使得能够有效的线程切换，从而提高处理速度。

公开(公告)号：US20060026594A1

公开(公告)日：2006-02-02

申请号：US10981772

申请日：2004-11-05

申请人： Toshio Yoshida ,  Masaki Ukai ,  Naohiro Kiyota

发明人： Toshio Yoshida ,  Masaki Ukai ,  Naohiro Kiyota

IPC分类号： G06F9/46

CPC分类号： G06F12/0859 ,  G06F9/3824 ,  G06F9/3851 ,  G06F12/0811 ,  G06F12/0842

摘要： The present invention relates to a multithread processor. In the multithread processor, when a cache miss occurs on a request related to an instruction in, of a plurality of caches arranged hierarchically, a cache at the lowest place in the hierarchy, with respect to the request suffering the cache miss, a cache control unit notifies an instruction identifier and a thread identifier, which are related to the instruction, to a multithread control unit. When a cache miss occurs on an instruction to be next completed, the multithread control unit makes the switching between threads on the basis of the instruction identifier and thread identifier notified from the cache control unit. This enables effective thread switching, thus enhancing the processing speed.

摘要翻译： 多线程处理器技术领域本发明涉及一种多线程处理器。 在多线程处理器中，当在与分级排列的多个高速缓存中的指令相关的请求上发生高速缓存未命中时，相对于遭受高速缓存未命中的请求，层级中的最低位置处的高速缓存，高速缓存控制 单元将与指令相关的指令标识符和线程标识符通知给多线程控制单元。 当在接下来完成的指令上发生高速缓存未命中时，多线程控制单元基于从缓存控制单元通知的指令标识符和线程标识符进行线程之间的切换。 这使得能够有效的线程切换，从而提高处理速度。

公开(公告)号：US08677070B2

公开(公告)日：2014-03-18

申请号：US12654312

申请日：2009-12-16

申请人： Naohiro Kiyota

发明人： Naohiro Kiyota

IPC分类号： G06F12/00

CPC分类号： G06F12/127 ,  G06F12/0859 ,  G06F12/1054

摘要： According to an aspect of the embodiment, an FP includes a plurality of entries which holds requests to be processed, and each of the plurality of entries includes a requested flag indicating that data transfer is once requested. An FP-TOQ holds information indicating an entry holding the oldest request. A data transfer request prevention determination circuit checks the requested flag of a request to be processed and the FP-TOQ, and when a transfer request of data as a target of the request to be processed has already been issued and the entry holding the request to be processed is not the entry indicated by the FP-TOQ, transmits a signal which prevents the transfer request of the data to a data transfer request control circuit. Even when a cache miss occurs in a primary cache RAM, the data transfer request control circuit does not issue a data transfer request when the signal which prevents the transfer request is received.

摘要翻译： 根据本实施例的一个方面，一种FP包括保存要处理的请求的多个条目，并且多个条目中的每个条目包括指示一次请求数据传送的请求标志。 FP-TOQ保存指示保存最早请求的条目的信息。 数据传输请求防止确定电路检查要处理的请求的请求的标志和FP-TOQ，并且当已经发出作为要处理的请求的目标的数据的传送请求和保持请求的条目 被处理的不是FP-TOQ指示的条目，所以发送防止数据传送请求到数据传送请求控制电路的信号。 即使在主缓存RAM中出现高速缓存未命中的情况下，当接收到阻止转移请求的信号时，数据传送请求控制电路也不会发出数据传输请求。

公开(公告)号：US20090055687A1

公开(公告)日：2009-02-26

申请号：US12222305

申请日：2008-08-06

申请人： Naohiro Kiyota

发明人： Naohiro Kiyota

IPC分类号： G06F11/07

CPC分类号： G11C29/56 ,  G06F11/1032 ,  G11C2029/0407

摘要： A RAM diagnosis device sequentially generates a state bit indicating any one of states of kinds of processing; selects processing referring to the state bit. The devices then writes a first data pattern in all areas of the RAM when writing processing is selected, and writes a second data pattern obtained by inverting the first data pattern in all the areas of the RAM when the writing processing is selected. The first data pattern is binary data. The device also reads out the first or the second data pattern from all the areas of the RAM to detect an error when error check processing is selected after each of the kinds of writing processing.

摘要翻译： RAM诊断装置顺序地生成指示处理种类的状态中的任何一种的状态位; 参考状态位选择处理。 然后，当选择写入处理时，器件在RAM的所有区域中写入第一数据模式，并且当选择写入处理时，写入通过将RAM中的所有区域中的第一数据模式反相而获得的第二数据模式。 第一个数据模式是二进制数据。 该设备还从RAM的所有区域读出第一或第二数据模式，以便在每种写入处理之后选择错误检查处理时检测错误。

公开(公告)号：US20100100710A1

公开(公告)日：2010-04-22

申请号：US12654380

申请日：2009-12-17

申请人： Naohiro Kiyota

发明人： Naohiro Kiyota

IPC分类号： G06F9/312 ,  G06F12/08

CPC分类号： G06F12/0855 ,  G06F9/3834 ,  G06F9/3851

摘要： According to an aspect of the embodiment, when data on a cache RAM is rewritten in a storage processing of one thread, an determination unit searches a fetch port which holds a request of another thread, checks whether a request exists whose processing is completed, whose instruction is a load type instruction, and whose target address corresponds to a target address in a storage processing. When the corresponding request is detected, the determination unit sets a re-execution request flag to all the entries of the fetch port from the next entry of the entry which holds the oldest request to the entry which holds the detected request. When the processing of the oldest request is executed, a re-execution request unit transfers a re-execution request of an instruction to an instruction control unit for the request held in the entry in which the re-execution request flag is set.

摘要翻译： 根据本实施方式的一个方面，当在一个线程的存储处理中重写高速缓冲存储器RAM的数据时，确定单元搜索保持另一线程的请求的取出端口，检查是否存在其处理完成的请求， 指令是负载类型指令，其目标地址对应于存储处理中的目标地址。 当检测到相应的请求时，确定单元从保存最早请求的条目的下一个条目向保存检测到的请求的条目的所有获取端口条目设置重新执行请求标志。 当执行最旧的请求的处理时，重新执行请求单元将指令的重新执行请求传送到设置了重新执行请求标志的条目中保存的请求的指令控制单元。

公开(公告)号：US20100088550A1

公开(公告)日：2010-04-08

申请号：US12636619

申请日：2009-12-11

申请人： Hiroyuki IMAI ,  Naohiro Kiyota ,  Tsuyoshi Motokurumada

发明人： Hiroyuki IMAI ,  Naohiro Kiyota ,  Tsuyoshi Motokurumada

IPC分类号： G06F11/00 ,  G06F12/00 ,  G06F12/08

CPC分类号： G06F12/0895 ,  G11C29/808

摘要： A cache memory apparatus is configured to include a data holding unit comprising a plurality of ways that has a plurality of cache lines; an alternation data register to hold data in one line of the cache lines or in a part of the cache lines; an alternation address register to hold an index address that indicates a faulty cache line and a part in which the fault has occurred in the faulty cache line; an alternation way register to hold information of a way including the part having a fault; an address match circuit comparing, when an access is performed to the data holding unit, an index address and the index address held by the alternation address register; and a way match circuit comparing, when an access is performed to the data holding unit, way information used for the access and way information held by the alternation way register.

摘要翻译： 高速缓冲存储器装置被配置为包括数据保持单元，该数据保持单元包括具有多个高速缓存线的多个路径; 交替数据寄存器，用于将数据保存在高速缓存行的一行或高速缓存行的一部分中; 交替地址寄存器，用于保存指示故障高速缓存行的索引地址和故障高速缓存行中发生故障的部分; 交替方式寄存器，用于保存包括具有故障的部分的方式的信息; 地址匹配电路，当对所述数据保持单元执行访问时，比较由所述交替地址寄存器保存的索引地址和索引地址; 以及方法匹配电路，当对数据保持单元执行访问时，比较用于由交替方式寄存器保存的访问和路径信息的路径信息。

公开(公告)号：US08412886B2

公开(公告)日：2013-04-02

申请号：US12654310

申请日：2009-12-16

申请人： Naohiro Kiyota

发明人： Naohiro Kiyota

IPC分类号： G06F13/18 ,  G06F12/00

CPC分类号： G06F12/0842 ,  G06F12/084 ,  G06F12/0855 ,  G06F2212/1048

摘要： In such a configuration that a port unit is provided which takes a form being shared among threads and has a plurality of entries for holding access requests, and the access requests for a cache shared by a plurality of threads being executed at the same time are controlled using the port unit, the access request issued from each tread is registered on a port section of the port unit which is assigned to the tread, thereby controlling the port unit to be divided for use in accordance with the thread configuration. In selecting the access request, the access requests are selected for each thread based on the specified priority control from among the access requests issued from the threads held in the port unit, thereafter a final access request is selected in accordance with a thread selection signal from among those selected access requests. In accordance with such a configuration, the cache access processing can be carried out while reducing the amount of resources of the port unit and assuring effective use of such resources.

摘要翻译： 在这样的配置中，提供了一种端口单元，其采用在线程之间共享的形式，并且具有用于保持访问请求的多个条目，并且控制由同时执行的多个线程共享的高速缓存的访问请求 使用端口单元，将从每个线程发出的访问请求登记在分配给线程的端口单元的端口部分上，从而根据线程配置来控制端口单元被划分使用。 在选择访问请求时，基于从保存在端口单元中的线程发出的访问请求中的基于指定的优先级控制为每个线程选择访问请求，此后根据来自 在这些选定的访问请求中。 根据这种配置，可以在减少端口单元的资源量并且确保有效地使用这种资源的同时进行高速缓存访​​问处理。

公开(公告)号：US20100106913A1

公开(公告)日：2010-04-29

申请号：US12654312

申请日：2009-12-16

申请人： Naohiro Kiyota

发明人： Naohiro Kiyota

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/127 ,  G06F12/0859 ,  G06F12/1054

摘要： According to an aspect of the embodiment, an FP includes a plurality of entries which holds requests to be processed, and each of the plurality of entries includes a requested flag indicating that data transfer is once requested. An FP-TOQ holds information indicating an entry holding the oldest request. A data transfer request prevention determination circuit checks the requested flag of a request to be processed and the FP-TOQ, and when a transfer request of data as a target of the request to be processed has already been issued and the entry holding the request to be processed is not the entry indicated by the FP-TOQ, transmits a signal which prevents the transfer request of the data to a data transfer request control circuit. Even when a cache miss occurs in a primary cache RAM, the data transfer request control circuit does not issue a data transfer request when the signal which prevents the transfer request is received.

摘要翻译： 根据本实施例的一个方面，一种FP包括保存要处理的请求的多个条目，并且多个条目中的每个条目包括指示一次请求数据传送的请求标志。 FP-TOQ保存指示保存最早请求的条目的信息。 数据传输请求防止确定电路检查要处理的请求的请求的标志和FP-TOQ，并且当已经发出作为要处理的请求的目标的数据的传送请求和保持请求的条目 被处理的不是FP-TOQ指示的条目，所以发送防止数据传送请求到数据传送请求控制电路的信号。 即使在主缓存RAM中出现高速缓存未命中的情况下，当接收到阻止转移请求的信号时，数据传送请求控制电路也不会发出数据传输请求。

公开(公告)号：US07437519B2

公开(公告)日：2008-10-14

申请号：US11283832

申请日：2005-11-22

申请人： Naohiro Kiyota ,  Iwao Yamazaki

发明人： Naohiro Kiyota ,  Iwao Yamazaki

IPC分类号： G06F12/14

CPC分类号： G06F9/52 ,  G06F9/3004 ,  G06F9/30087 ,  G06F9/3009 ,  G06F12/0815 ,  Y02D10/13

摘要： A multithread control apparatus and control method to switch a plurality of threads in a multithread processor, which includes a plurality of thread processors to execute the plurality of threads, by executing a synchronization lock control by considering release of exclusive access right to a relevant thread processor when a particular block in caches is updated with another processor or another thread processor during execution of a certain thread processor.

摘要翻译： 一种多线程控制装置和控制方法，用于通过考虑发布对相关线程处理器的独占访问权限来执行同步锁定控制来切换包括多个线程处理器以执行多个线程的多线程处理器中的多个线程 当在某个线程处理器执行期间，缓存中的特定块被另一个处理器或另一个线程处理器更新。

公开(公告)号：US08700947B2

公开(公告)日：2014-04-15

申请号：US12636619

申请日：2009-12-11

申请人： Hiroyuki Imai ,  Naohiro Kiyota ,  Tsuyoshi Motokurumada

发明人： Hiroyuki Imai ,  Naohiro Kiyota ,  Tsuyoshi Motokurumada

IPC分类号： G06F11/00

CPC分类号： G06F12/0895 ,  G11C29/808

摘要： A cache memory apparatus is configured to include a data holding unit comprising a plurality of ways that has a plurality of cache lines; an alternation data register to hold data in one line of the cache lines or in a part of the cache lines; an alternation address register to hold an index address that indicates a faulty cache line and a part in which the fault has occurred in the faulty cache line; an alternation way register to hold information of a way including the part having a fault; an address match circuit comparing, when an access is performed to the data holding unit, an index address and the index address held by the alternation address register; and a way match circuit comparing, when an access is performed to the data holding unit, way information used for the access and way information held by the alternation way register.

摘要翻译： 高速缓冲存储器装置被配置为包括数据保持单元，该数据保持单元包括具有多个高速缓存线的多个路径; 交替数据寄存器，用于将数据保存在高速缓存行的一行或高速缓存行的一部分中; 交替地址寄存器，用于保存指示故障高速缓存行的索引地址和故障高速缓存行中发生故障的部分; 交替方式寄存器，用于保存包括具有故障的部分的方式的信息; 地址匹配电路，当对所述数据保持单元执行访问时，比较由所述交替地址寄存器保存的索引地址和索引地址; 以及方式匹配电路，当对数据保持单元执行访问时，比较用于由交替方式寄存器保持的访问和路径信息的路径信息。