公开(公告)号：US20230255016A1

公开(公告)日：2023-08-10

申请号：US18133929

申请日：2023-04-12

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: H10B12/00 ,  H01L27/06 ,  G11C11/408 ,  G11C11/22 ,  H01L29/786 ,  H10B53/20

CPC classification number: H10B12/30 ,  H01L27/0688 ,  G11C11/408 ,  G11C11/2253 ,  G11C11/221 ,  H01L29/78642 ,  H10B53/20

Abstract: Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.

公开(公告)号：US11659705B2

公开(公告)日：2023-05-23

申请号：US17327042

申请日：2021-05-21

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/24 ,  H01L27/108 ,  H01L27/06 ,  H01L27/11514 ,  G11C11/408 ,  G11C11/22 ,  H01L29/786

CPC classification number: H01L27/10805 ,  G11C11/221 ,  G11C11/2253 ,  G11C11/408 ,  H01L27/0688 ,  H01L27/11514 ,  H01L29/78642

Abstract: Methods, systems, and devices for thin film transistor deck selection in a memory device are described. A memory device may include memory arrays arranged in a stack of decks formed over a substrate, and deck selection components distributed among the layers to leverage common substrate-based circuitry. For example, each memory array of the stack may include a set of digit lines of a corresponding deck, and deck selection circuitry operable to couple the set of digit lines with a column decoder that is shared among multiple decks. To access memory cells of a selected memory array on one deck, the deck selection circuitry corresponding to the memory array may each be activated, while the deck selection circuitry corresponding to a non-selected memory array on another deck may be deactivated. The deck selection circuitry, such as transistors, may leverage thin-film manufacturing techniques, such as various techniques for forming vertical transistors.

公开(公告)号：US20220172765A1

公开(公告)日：2022-06-02

申请号：US17675686

申请日：2022-02-18

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22

Abstract: Methods, systems, and devices for memory array with multiplexed select lines are described. In some cases, a memory cell of the memory device may include a storage component, a first transistor coupled with a word line, and a second transistor coupled with a first select line to selectively couple the memory cell with a first digit line. A third transistor may be coupled with the first digit line and a sense component common to a set of digit lines and a set of select lines. A second select line may be coupled with the third transistor and configured to couple the sense component with the first digit line and to couple the sense component with a second digit line. The sense component may determine a logic state stored by the memory cell based on the signal from the first digit line and the signal from the second digit line.

公开(公告)号：US11335644B2

公开(公告)日：2022-05-17

申请号：US16563691

申请日：2019-09-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo ,  Daniele Vimercati

IPC: H01L23/552 ,  H01L23/528 ,  H01L27/11507 ,  G11C11/22 ,  G11C11/4091 ,  G11C11/409 ,  G11C11/408 ,  G11C11/4094 ,  G11C13/00 ,  G11C11/16 ,  H01L27/108 ,  G11C7/10 ,  G11C7/08 ,  H01L27/11514

Abstract: Apparatuses and methods for memory that includes a first memory cell including a storage component having a first end coupled to a plate line and a second end coupled to a digit line, and a second memory cell including a storage component having a first end coupled to a digit line and a second end coupled to a plate line, wherein the digit line of the second memory cell is adjacent to the plate line of the first memory cell.

公开(公告)号：US11244715B1

公开(公告)日：2022-02-08

申请号：US17108268

申请日：2020-12-01

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22

Abstract: Memory cells are described that include two reference voltages that may store and sense three distinct memory states by compensating for undesired intrinsic charges affecting a memory cell. Although embodiments described herein refer to three memory states, it should be appreciated that in other embodiments, the memory cell may store or sense more than three charge distributions using the described methods and techniques. In a first memory state, a programming voltage or a sensed voltage may be higher than a first reference voltage and a second reference voltage. In a second memory state, the applied voltage or the sensed voltage may be between the first and the second reference voltages. In a third memory state, the applied voltage or the sensed voltage may be lower than the first and the second reference voltages. As such, the memory cell may store and retrieve three memory states.

公开(公告)号：US20210375892A1

公开(公告)日：2021-12-02

申请号：US17347462

申请日：2021-06-14

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: H01L27/11514 ,  G11C11/22 ,  H01L27/11507 ,  G11C5/02

Abstract: Methods, systems, and devices for plate node configurations and operations for a memory array are described. A single plate node of a memory array may be coupled to multiple rows or columns of memory cells (e.g., ferroelectric memory cells) in a deck of memory cells. The single plate node may perform the functions of multiple plate nodes. The number of contacts to couple the single plate node to the substrate may be less than the number of contacts to couple multiple plate nodes to the substrate. Connectors or sockets in a memory array with a single plate node may define a size that is less than a size of the connectors or sockets with multiple plate nodes. In some examples, a single plate node of the memory array may be coupled to multiple lines of a memory cells in multiple decks of memory cells.

公开(公告)号：US20210304804A1

公开(公告)日：2021-09-30

申请号：US16831116

申请日：2020-03-26

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22

Abstract: Methods, systems, and devices for memory array with multiplexed select lines are described. In some cases, a memory cell of the memory device may include a storage component, a first transistor coupled with a word line, and a second transistor coupled with a first select line to selectively couple the memory cell with a first digit line. A third transistor may be coupled with the first digit line and a sense component common to a set of digit lines and a set of select lines. A second select line may be coupled with the third transistor and configured to couple the sense component with the first digit line and to couple the sense component with a second digit line. The sense component may determine a logic state stored by the memory cell based on the signal from the first digit line and the signal from the second digit line.

公开(公告)号：US20210098045A1

公开(公告)日：2021-04-01

申请号：US17118800

申请日：2020-12-11

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22

Abstract: Methods, systems, and devices for access line management for an array of memory cells are described. Some memory devices may include a plate that is coupled with memory cells associated with a plurality of digit lines and/or a plurality of word lines. Because the plate is coupled with a plurality of digit lines and/or word lines, unintended cross-coupling between various components of the memory device may be significant. To mitigate the impact of unintended cross-coupling between various components, the memory device may float unselected word lines during one or more portions of an access operation. Accordingly, a voltage of each unselected word line may relate to the voltage of the plate as changes in plate voltage may occur.

公开(公告)号：US20210050046A1

公开(公告)日：2021-02-18

申请号：US17072566

申请日：2020-10-16

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22 ,  G11C11/00 ,  G11C14/00

Abstract: Methods, systems, and devices for dual mode ferroelectric memory cell operation are described. A memory array or portions of the array may be variously operated in volatile and non-volatile modes. For example, a memory cell may operate in a non-volatile mode and then operate in a volatile mode following a command initiated by a controller while the cell is operating in the non-volatile mode. The memory cell may operate in the volatile mode and then operate in the non-volatile mode following a subsequent command. In some examples, one memory cell of the memory array may operate in the non-volatile mode while another memory cell of the memory array operates in the volatile mode.

公开(公告)号：US10902901B2

公开(公告)日：2021-01-26

申请号：US16701006

申请日：2019-12-02

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati

IPC: G11C11/22

Abstract: Methods, systems, and devices for access line management for an array of memory cells are described. Some memory devices may include a plate that is coupled with memory cells associated with a plurality of digit lines and/or a plurality of word lines. Because the plate is coupled with a plurality of digit lines and/or word lines, unintended cross-coupling between various components of the memory device may be significant. To mitigate the impact of unintended cross-coupling between various components, the memory device may float unselected word lines during one or more portions of an access operation. Accordingly, a voltage of each unselected word line may relate to the voltage of the plate as changes in plate voltage may occur.