公开(公告)号：US11074982B2

公开(公告)日：2021-07-27

申请号：US16989191

申请日：2020-08-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca De Santis

IPC: G11C16/26 ,  G06N3/04 ,  G06N3/063 ,  G11C7/10 ,  G11C16/08 ,  G11C16/04

Abstract: Memory having an array of memory cells and configured to store a first value representative of a characteristic sensed from a first data line, store a second value representative of the characteristic sensed from a second data line, perform an operation on the first value and the data value at a first logic circuitry, and perform an operation on an output of the first logic circuitry and a threshold data value at a second logic circuitry.

公开(公告)号：US20210210143A1

公开(公告)日：2021-07-08

申请号：US17206827

申请日：2021-03-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/34 ,  G11C16/26

Abstract: Memories might include control logic configured to cause the memory to perform a first sense operation having an initial phase and a plurality of sensing phases on a first grouping of memory cells, pause the first sense operation upon completion of a present sensing phase in response to receiving a command to perform a second sense operation on a second grouping of memory cells while performing the present sensing phase, perform an initial phase of the second sense operation after pausing the first sense operation, and, in response to completion of the initial phase of the second sense operation, resume the first sense operation at a next subsequent sensing phase of the plurality of sensing phases and continue to a sensing phase of the second sense operation to perform the next subsequent sensing phase of the first sense operation and the sensing phase of the second sense operation concurrently.

公开(公告)号：US20210103389A1

公开(公告)日：2021-04-08

申请号：US17123472

申请日：2020-12-16

Applicant: Micron Technology, Inc.

Inventor： Sivagnanam Parthasarathy ,  Terry M. Grunzke ,  Lucia Botticchio ,  Walter Di Francesco ,  Vamshi K. Indavarapu ,  Gianfranco Valeri ,  Renato C. Padilla ,  Ali Mohammadzadeh ,  Jung Sheng Hoei ,  Luca De Santis

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1009

Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.

公开(公告)号：US10770152B2

公开(公告)日：2020-09-08

申请号：US16180137

申请日：2018-11-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca De Santis ,  Tommaso Vali

IPC: G11C16/28 ,  G11C15/00 ,  G11C15/04 ,  G11C16/04

Abstract: Methods of operating a memory device include comparing input data to data stored in strings of series-connected memory cells coupled to a data line, generating a respective resistance in series with each string of series-connected memory cells while comparing the plurality of digits of input data to the stored data, comparing a representation of a level of current in the data line to a reference, deeming the input data to match the stored data in response to the representation of the level of current in the data line being less than the reference, and deeming the input data to not match the stored data in response to the representation of the level of current in the data line being greater than the reference.

公开(公告)号：US10741258B2

公开(公告)日：2020-08-11

申请号：US16515134

申请日：2019-07-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca De Santis

IPC: G11C16/26 ,  G06N3/04 ,  G06N3/063 ,  G11C7/10 ,  G11C16/08 ,  G11C16/04

Abstract: Memory having an array of memory cells and a controller for access of the array of memory cells that is configured to generate a data value indicative of a level of a property sensed from a data line while applying potentials to control gates of memory cells of more than one string of series-connected memory cells connected to that data line.

公开(公告)号：US10714191B2

公开(公告)日：2020-07-14

申请号：US16410406

申请日：2019-05-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Luca De Santis ,  Ramin Ghodsi

IPC: G11C16/26 ,  G11C11/56 ,  G06F11/07 ,  G11C29/02 ,  G11C16/04 ,  G11C29/24

Abstract: Methods of operating a memory include determining a voltage level of a plurality of voltage levels at which a memory cell is deemed to first activate in response to applying the to a control gate of that memory cell for each memory cell of a plurality of memory cells, determining a plurality of voltage level distributions from numbers of memory cells of a first subset of memory cells deemed to first activate at each voltage level of the plurality of voltage levels, determining a transition between a pair of voltage level distributions for each adjacent pair of voltage level distributions, and assigning a respective data state to each memory cell of a second subset of memory cells responsive to the determined voltage level at which that memory cell is deemed to first activate and respective voltage levels of the transitions for each adjacent pair of voltage level distributions.

公开(公告)号：US20190272877A1

公开(公告)日：2019-09-05

申请号：US16413708

申请日：2019-05-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge ,  Frankie F. Roohparvar

IPC: G11C16/10 ,  G11C16/04

Abstract: Memories include a data line, a plurality of strings of series-connected memory cells selectively connected to the data line, a plurality of first access lines each coupled to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells, and a plurality of second access lines each coupled to a control gate of a respective memory cell of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells.

公开(公告)号：US10403371B2

公开(公告)日：2019-09-03

申请号：US16009541

申请日：2018-06-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca De Santis

IPC: G11C16/26 ,  G06N3/04 ,  G06N3/063 ,  G11C16/04 ,  G11C7/10 ,  G11C16/08

Abstract: Methods of operating memory include generating a data value indicative of a level of a property sensed from a data line while applying potentials to control gates of memory cells of more than one string of series-connected memory cells connected to that data line. Methods of operating memory further include generating data values indicative of levels of a property sensed from data lines while applying potentials to control gates of memory cells of strings of series-connected memory cells connected to those data lines, performing a logical operation on a set of data values comprising those data values, and determining a potential to be applied to control gates of different memory cells of those strings of series-connected memory cells in response to an output of the logical operation on the set of data values.

公开(公告)号：US10388384B2

公开(公告)日：2019-08-20

申请号：US16043259

申请日：2018-07-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Luca De Santis ,  Ramin Ghodsi

IPC: G11C11/56 ,  G11C16/26 ,  G06F11/07 ,  G11C29/02 ,  G11C16/04 ,  G11C29/24

Abstract: Methods of operating a memory include determining a voltage level of a plurality of voltage levels at which a memory cell is deemed to first activate in response to applying the to a control gate of that memory cell for each memory cell of a plurality of memory cells, determining a plurality of voltage level distributions from numbers of memory cells of a first subset of memory cells deemed to first activate at each voltage level of the plurality of voltage levels, determining a transition between a pair of voltage level distributions for each adjacent pair of voltage level distributions, and assigning a respective data state to each memory cell of a second subset of memory cells responsive to the determined voltage level at which that memory cell is deemed to first activate and respective voltage levels of the transitions for each adjacent pair of voltage level distributions.

公开(公告)号：US10332605B2

公开(公告)日：2019-06-25

申请号：US15645009

申请日：2017-07-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca De Santis ,  Tommaso Vali

IPC: G11C15/00 ,  G11C16/28 ,  G11C15/04 ,  G11C16/04

Abstract: Methods of operating a memory device include comparing input data to data stored in memory cells coupled to a data line, comparing a representation of a level of current in the data line to a reference, and determining that the input data potentially matches the data stored in the memory cells when the representation of the level of current in the data line is less than the reference. Methods of operating a memory device further include comparing input data to first data and to second data stored in memory cells coupled to a first data line or to a second data line, respectively, comparing representations of the levels of current in the first data line and in the second data line to a first reference and to a different second reference, and deeming one to be a closer match to the input data in response to results of the comparisons.